Datasheet GigaDevice GD32E503CET6

GD32E503xx Datasheet GigaDevice Semiconductor Inc.
GD32E503xx
Arm® Cortex®-M33 32-bit MCU Datasheet GD32E503xx Datasheet Table of Contents
Table of Contents . 1
List of Figures . 4
List of Tables . 5
1. General description . 7
2. Device overview . 8
2.1. Device information . 8 2.2. Block diagram . 9 2.3. Pinouts and pin assignment . 10 2.4. Memory map . 13 2.5. Clock tree . 17 2.6. Pin definitions . 18 2.6.1. GD32E503Zx LQFP144 pin definitions . 18 2.6.2. GD32E503Vx LQFP100 pin definitions . 28 2.6.3. GD32E503Rx LQFP64 pin definitions . 35 2.6.4. GD32E503Cx LQFP48 pin definitions . 40 3. Functional description . 44
3.1. Arm® Cortex®-M33 core . 44 3.2. Embedded memory . 44 3.3. Clock, reset and supply management . 45 3.4. Boot modes . 45 3.5. Power saving modes . 46 3.6. Analog to digital converter (ADC) . 47 3.7. Digital to analog converter (DAC) . 47 3.8. DMA . 47 3.9. General-purpose inputs/outputs (GPIOs) . 48 3.10. Timers and PWM generation . 48 3.11. Real time clock (RTC) . 49 3.12. Inter-integrated circuit (I2C) . 50 3.13. Serial peripheral interface (SPI) . 50 3.14. Universal synchronous asynchronous receiver transmitter (USART) . 51
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3.15. Inter-IC sound (I2S) . 51 3.16. Universal Serial Bus full-speed device interface (USBD) . 51 3.17. Controller area network (CAN) . 52 3.18. External memory controller (EXMC) . 52 3.19. Secure digital input/output interface (SDIO) . 52 3.20. Super High-Resolution Timer (SHRTIMER) . 53 3.21. Serial/Quad Parallel Interface (SQPI) . 53 3.22. Debug mode . 53 3.23. Package and operation temperature . 53 4. Electrical characteristics . 54
4.1. Absolute maximum ratings . 54 4.2. Operating conditions characteristics . 54 4.3. Power consumption . 56 4.4. EMC characteristics . 65 4.5. Power supply supervisor characteristics . 65 4.6. Electrical sensitivity . 66 4.7. External clock characteristics . 67 4.8. Internal clock characteristics . 69 4.9. PLL characteristics. 70 4.10. Memory characteristics . 72 4.11. NRST pin characteristics . 72 4.12. GPIO characteristics . 73 4.13. Temperature sensor characteristics . 74 4.14. ADC characteristics . 75 4.15. DAC characteristics . 77 4.16. I2C characteristics . 78 4.17. SPI characteristics . 78 4.18. I2S characteristics. 79 4.19. USART characteristics . 80 4.20. CAN characteristics . 80 4.21. USBD characteristics . 80 4.22. SDIO characteristics . 82
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4.23. EXMC characteristics. 82 4.24. Serial/Quad Parallel Interface (SQPI) characteristics . 86 4.25. Super High-Resolution Timer (SHRTIMER) characteristics . 87 4.26. TIMER characteristics …

GigaDevice Semiconductor Inc.
GD32E50x
Arm® Cortex®-M33 32-bit MCU User Manual
Revision 1.0
(Jul. 2020) GD32E50x User Manual Table of Contents
Table of Contents . 2
List of Figures . 21
List of Tables . 31
1. System and memory architecture . 36
1.1. Arm® Cortex®-M33 processor . 36 1.2. System architecture . 37 1.3. Memory map . 39 1.3.1. Bit-banding . 43 1.3.2. On-chip SRAM memory . 44 1.3.3. On-chip flash memory overview . 44 1.4. Boot configuration . 44 1.5. Device electronic signature . 45 1.5.1. Memory density information. 45 1.5.2. Unique device ID (96 bits) . 46 1.6. System configuration registers . 47 2. Flash memory controller (FMC) . 48
2.1. Overview . 48 2.2. Characteristics . 48 2.3. Function overview. 48 2.3.1. Flash memory architecture . 48 2.3.2. Read operations . 49 2.3.3. Unlock the FMC_CTL register . 50 2.3.4. Page erase. 51 2.3.5. Mass erase . 52 2.3.6. Main flash programming . 53 2.3.7. OTP programming . 55 2.3.8. Option bytes erase . 55 2.3.9. Option bytes modify . 56 2.3.10. Option bytes description . 56 2.3.11. Page erase / program protection . 58 2.3.12. Security protection . 58 2.4. Register definition. 59 2.4.1. Wait state register (FMC_WS) . 59 2.4.2. Unlock key register (FMC_KEY) . 60 2.4.3. Option byte unlock key register (FMC_OBKEY) . 60
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2.4.4. Status register (FMC_STAT) . 61 2.4.5. Control register (FMC_CTL) . 62 2.4.6. Address register (FMC_ADDR) . 63 2.4.7. Option byte status register (FMC_OBSTAT). 63 2.4.8. Erase/Program protection register (FMC_WP). 64 2.4.9. Product ID register (FMC_PID). 64 3. Backup registers (BKP) . 66
3.1. Overview . 66 3.2. Characteristics . 66 3.3. Function overview. 66 3.3.1. RTC clock calibration . 66 3.3.2. Tamper detection . 66 3.4. Register definition. 68 3.4.1. Backup data register x (BKP_DATAx) (x= 0.41) . 68 3.4.2. RTC signal output control register (BKP_OCTL) . 68 3.4.3. Tamper pin control register (BKP_TPCTL) . 69 3.4.4. Tamper control and status register (BKP_TPCS) . 70 4. Power management unit (PMU) . 71
4.1. Overview . 71 4.2. Characteristics . 71 4.3. Function overview. 72 4.3.1. Battery backup domain . 72 4.3.2. VDD/VDDA power domain . 73 4.3.3. 1.1V power domain . 76 4.3.4. Power saving modes . 76 4.4. Register definition. 81 4.4.1. Control register 0 (PMU_CTL0) . 81 4.4.2. Control and status register 0 (PMU_CS0) . 83 4.4.3. Control register 1 (PMU_CTL1) . 85 4.4.4. Control and status register 1 (PMU_CS1) . 86 5. Reset and clock unit (RCU) . 87
High-and Extra-density Reset and clock control unit (RCU). 87
5.1. Reset control unit (RCTL) . 87 5.1.1. Overview . …