Datasheet AD711 (Analog Devices) - 9

AD711 OP AMP SETTLING TIME—A MATHEMATICAL MODEL
op amp is being simulated or it is the combined capacitance of The design of the AD711 gives careful attention to optimizing the DAC output and the op amp input if the DAC buffer is individual circuit components; in addition, a careful tradeoff was being modeled. made: the gain bandwidth product (4 MHz) and slew rate (20 V/ms) were chosen to be high enough to provide very fast settling time but not too high to cause a significant reduction in phase margin (and therefore stability). Thus designed, the AD711
AD711 VOUT
settles to ± 0.01%, with a 10 V output step, in under 1 ms, while
CF RL CL
retaining the ability to drive a 100 pF load capacitance when operating as a unity gain follower.
RIN R
If an op amp is modeled as an ideal integrator with a unity gain crossover frequency of w
VIN C
o/2p, Equation 1 will accurately describe
X
the small signal behavior of the circuit of Figure 3a, consisting of an op amp connected as an I-to-V converter at the output of a Figure 3b. Simplified Model of the AD711 bipolar or CMOS DAC. This equation would completely describe Used as an Inverter the output of the system if not for the op amp’s finite slew rate and other nonlinear effects. In either case, the capacitance CX causes the system to go from a one-pole to a two-pole response; this additional pole increases V settling time by introducing peaking or ringing in the op amp O = – R I R(C = C ) output. Since the value of C IN f X Ê ˆ X can be estimated with reasonable w s2 + GN ËÁ w + RCf ¯˜ s +1 (3) accuracy, Equation 2 can be used to choose a small capacitor, o o CF, to cancel the input pole and optimize amplifier response. Figure 4 is a graphical solution of Equation 2 for the AD711 where: w with R = 4 kW. o =op amp’s unity gain frequency 2p Ê ˆ
60
G 1 + R
G
N = “noise” gain of circuit ËÁ
N = 4.0
R ¯˜ O
50 G
This equation may then be solved for C
N = 3.0
f:
GN = 2.0 40
w ) C = 2 - GN + 2 RCX o + (1 - GN (3) f Rwo Rwo
XC 30 G
In these equations, capacitor C
N = 1.5
X is the total capacitor appearing the inverting terminal of the op amp. When modeling a DAC
20
buffer application, the Norton equivalent circuit of Figure 3a
GN = 1.0
can be used directly; capacitance CX is the total capacitance of
10
the output of the DAC plus the input capacitance of the op amp (since the two are in parallel).
0 0 10 20 30 40 50 60 CF
Figure 4. Value of Capacitor CF vs. Value of CX
AD711 VOUT
The photos of Figures 5a and 5b show the dynamic response of
CF RL CL
the AD711 in the settling test circuit of Figure 6. The input of the settling time fixture is driven by a flat-top pulse
R
generator. The error signal output from the false summing node
IO R C
of A1 is clamped, amplified by A2 and then clamped again. The
O X
error signal is thus clamped twice: once to prevent overloading amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. The Tektronix oscilloscope preamp type Figure 3a. Simplified Model of the AD711 Used as a 7A26 was carefully chosen because it does not overload with Current-Out DAC Buffer these input levels. Amplifier A2 needs to be a very high speed When RO and IO are replaced with their Thevenin VIN and RIN FET-input op amp; it provides a gain of 10, amplifying the error equivalents, the general purpose inverting amplifier of Figure 26b signal output of A1. is created. Note that when using this general model, capacitance CX is either the input capacitance of the op amp if a simple inverting –8– REV. E Document Outline FEATURES PRODUCT DESCRIPTION CONNECTION DIAGRAMS PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Typical Performance Characteristics OPTIMIZING SETTLING TIME OP AMP SETTLING TIME—A MATHEMATICAL MODEL GUARDING D/A CONVERTER APPLICATIONS NOISE CHARACTERISTICS DRIVING THE ANALOG INPUT OF AN A/D CONVERTER DRIVING A LARGE CAPACITIVE LOAD ACTIVE FILTER APPLICATIONS SECOND ORDER LOW PASS FILTER 9-POLE CHEBYCHEV FILTER OUTLINE DIMENSIONS Revision History