Datasheet AD7708, AD7718 (Analog Devices) - 9

AD7708/AD7718 TIMING CHARACTERISTICS1, 2 (AVDD = 2.7 V to 3.6 V or AVDD = 5 V
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5%; DVDD = 2.7 V to 3.6 V or DVDD = 5 V
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5%; AGND = DGND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted. Limit at TMIN, TMAX Parameter (B Version) Unit Conditions/Comments
t1 32.768 kHz typ Crystal Oscillator Frequency t2 50 ns min RESET Pulsewidth Read Operation t3 0 ns min RDY to CS Setup Time t4 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 t 4 5 0 ns min SCLK Active Edge to Data Valid Delay3 60 ns max DVDD = 4.5 V to 5.5 V 80 ns max DVDD = 2.7 V to 3.6 V t 4, 5 5A 0 ns min CS Falling Edge to Data Valid Delay3 60 ns max DVDD = 4.5 V to 5.5 V 80 ns max DVDD = 2.7 V to 3.6 V t6 100 ns min SCLK High Pulsewidth t7 100 ns min SCLK Low Pulsewidth t8 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time3 t 6 9 10 ns min Bus Relinquish Time after SCLK Inactive Edge3 80 ns max t10 100 ns max SCLK Active Edge to RDY High3, 7 Write Operation t11 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 t12 30 ns min Data Valid to SCLK Edge Setup Time t13 25 ns min Data Valid to SCLK Edge Hold Time t14 100 ns min SCLK High Pulsewidth t15 100 ns min SCLK Low Pulsewidth t16 0 ns min CS Rising Edge to SCLK Edge Hold Time NOTES 1Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV DD) and timed from a voltage level of 1.6 V. 2See Figures 1 and 2. 3SCLK active edge is falling edge of SCLK. 4These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits. 5This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines. 6These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the load circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update. Specifications subject to change without notice.
I (1.6mA WITH DV SINK DD = 5V 100
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A WITH DVDD = 3V) TO OUTPUT 1.6V PIN 50pF ISOURCE (200
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A WITH DVDD = 5V 100
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A WITH DVDD = 3V)
Figure 1. Load Circuit for Timing Characterization REV. 0 –9–