Datasheet NCP1200 (ON Semiconductor) - 8
| Manufacturer | ON Semiconductor |
| Description | PWM Current-Mode Controller for Low-Power Universal Off-Line Supplies |
| Pages / Page | 16 / 8 — NCP1200. Skipping Cycle Mode. Figure 18. Output pulses at various power … |
| File Format / Size | PDF / 288 Kb |
| Document Language | English |
NCP1200. Skipping Cycle Mode. Figure 18. Output pulses at various power levels. (X = 5. ms/div) P1<P2<P3
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NCP1200
3. Permanently force the VCC level above VCCH with When FB is above the skip cycle threshold (1.4 V by an auxiliary winding. It will automatically default), the peak current cannot exceed 1 V/Rsense. When disconnect the internal startup source and the IC the IC enters the skip cycle mode, the peak current cannot go will be fully self−supplied from this winding. below Vpin1 / 4 (Figure 19). The user still has the flexibility Again, the total power drawn from the mains will to alter this 1.4 V by either shunting pin 1 to ground through significantly decrease. Make sure the auxiliary a resistor or raising it through a resistor up to the desired voltage never exceeds the 16 V limit. level.
Skipping Cycle Mode
The NCP1200 automatically skips switching cycles when the output power demand drops below a given level. This is
P1
accomplished by monitoring the FB pin. In normal operation, pin 2 imposes a peak current accordingly to the load value. If the load demand decreases, the internal loop
P2
asks for less peak current. When this setpoint reaches a determined level, the IC prevents the current from decreasing further down and starts to blank the output pulses: the IC enters the so−called skip cycle mode, also
P3
named controlled burst operation. The power transfer now depends upon the width of the pulse bunches (Figure 18 ). Suppose we have the following component values: Lp, primary inductance = 1 mH
Figure 18. Output pulses at various power levels (X = 5
F
ms/div) P1<P2<P3
SW, switching frequency = 48 kHz Ip skip = 300 mA (or 350 mV / Rsense) The theoretical power transfer is therefore: Max Peak Current 1 2 @ Lp @ Ip2 @ Fsw + 2.2 W If this IC enters skip cycle mode with a bunch length of 10 ms over a recurrent period of 100 ms, then the total power Skip Cycle transfer is: 2.2
.
0.1 = 220 mW. Current Limit To better understand how this skip cycle mode takes place, a look at the operation mode versus the FB level immediately gives the necessary insight: FB 4.8 V 3.8 V
Figure 19. The skip cycle takes place at low peak
Normal Current Mode Operation
currents which guarantees noise free operation
1.4 V Skip Cycle Operation Ipmin = 350 mV / Rsense
Figure 17. Feedback Voltage Variations www.onsemi.com 8
NCP1200
3. Permanently force the VCC level above VCCH with When FB is above the skip cycle threshold (1.4 V by an auxiliary winding. It will automatically default), the peak current cannot exceed 1 V/Rsense. When disconnect the internal startup source and the IC the IC enters the skip cycle mode, the peak current cannot go will be fully self−supplied from this winding. below Vpin1 / 4 (Figure 19). The user still has the flexibility Again, the total power drawn from the mains will to alter this 1.4 V by either shunting pin 1 to ground through significantly decrease. Make sure the auxiliary a resistor or raising it through a resistor up to the desired voltage never exceeds the 16 V limit. level.
Skipping Cycle Mode
The NCP1200 automatically skips switching cycles when the output power demand drops below a given level. This is
P1
accomplished by monitoring the FB pin. In normal operation, pin 2 imposes a peak current accordingly to the load value. If the load demand decreases, the internal loop
P2
asks for less peak current. When this setpoint reaches a determined level, the IC prevents the current from decreasing further down and starts to blank the output pulses: the IC enters the so−called skip cycle mode, also
P3
named controlled burst operation. The power transfer now depends upon the width of the pulse bunches (Figure 18 ). Suppose we have the following component values: Lp, primary inductance = 1 mH
Figure 18. Output pulses at various power levels (X = 5
F
ms/div) P1<P2<P3
SW, switching frequency = 48 kHz Ip skip = 300 mA (or 350 mV / Rsense) The theoretical power transfer is therefore: Max Peak Current 1 2 @ Lp @ Ip2 @ Fsw + 2.2 W If this IC enters skip cycle mode with a bunch length of 10 ms over a recurrent period of 100 ms, then the total power Skip Cycle transfer is: 2.2
.
0.1 = 220 mW. Current Limit To better understand how this skip cycle mode takes place, a look at the operation mode versus the FB level immediately gives the necessary insight: FB 4.8 V 3.8 V
Figure 19. The skip cycle takes place at low peak
Normal Current Mode Operation
currents which guarantees noise free operation
1.4 V Skip Cycle Operation Ipmin = 350 mV / Rsense
Figure 17. Feedback Voltage Variations www.onsemi.com 8
