Datasheet NCP1200 (ON Semiconductor) - 9
| Manufacturer | ON Semiconductor |
| Description | PWM Current-Mode Controller for Low-Power Universal Off-Line Supplies |
| Pages / Page | 16 / 9 — NCP1200. Power Dissipation. Overload Operation. www.onsemi.com |
| File Format / Size | PDF / 288 Kb |
| Document Language | English |
NCP1200. Power Dissipation. Overload Operation. www.onsemi.com
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NCP1200 Power Dissipation Overload Operation
The NCP1200 is directly supplied from the DC rail In applications where the output current is purposely not through the internal DSS circuitry. The current flowing controlled (e.g. wall adapters delivering raw DC level), it is through the DSS is therefore the direct image of the interesting to implement a true short−circuit protection. A NCP1200 current consumption. The total power dissipation short−circuit actually forces the output voltage to be at a low can be evaluated using: (V level, preventing a bias current to circulate in the HVDC * 11 V) @ ICC2. If we operate the device on a 250 VAC rail, the maximum rectified optocoupler LED. As a result, the FB pin level is pulled up voltage can go up to 350 VDC. As a result, the worse case to 4.1 V, as internally imposed by the IC. The peak current dissipation occurs on the 100 kHz version which will setpoint goes to the maximum and the supply delivers a dissipate 340
.
1.8 mA@Tj = −25° C = 612 mW (however rather high power with all the associated effects. Please note this 1.8 mA number will drop at higher operating that this can also happen in case of feedback loss, e.g. a temperatures). Please note that in the above example, ICC2 broken optocoupler. To account for this situation, the is based on a 1 nF capacitor loading pin 5. As seen before, NCP1200 hosts a dedicated overload detection circuitry. ICC2 will depend on your MOSFET’s Qg: ICC2 = ICC1 + Fsw Once activated, this circuitry imposes to deliver pulses in a x Qg. Final calculations shall thus account for the total burst manner with a low duty cycle. The system recovers gate−charge Qg your MOSFET will exhibit. A DIP8 when the fault condition disappears. package offers a junction−to−ambient thermal resistance During the startup phase, the peak current is pushed to the of RqJ−A 100° C/W. The maximum power dissipation can maximum until the output voltage reaches its target and the thus be computed knowing the maximum operating feedback loop takes over. This period of time depends on ambient temperature (e.g. 70° C) together with the normal output load conditions and the maximum peak maximum allowable junction temperature (125° C): current allowed by the system. The time−out used by this IC T works with the VCC decoupling capacitor: as soon as the Pmax + Jmax * TAmax = 550 mW. As we can see, we do not R V RqJ*A CC decreases from the VCCOFF level (typically 11.4 V) the reach the worse consumption budget imposed by the 100 device internally watches for an overload current situation. kHz version. Two solutions exist to cure this trouble. The If this condition is still present when VCCON is reached, the first one consists in adding some copper area around the controller stops the driving pulses, prevents the self−supply NCP1200 DIP8 footprint. By adding a min−pad area of 80 current source to restart and puts all the circuitry in standby, mm2 of 35 m copper (1 oz.) RqJ−A drops to about 75° C/W consuming as little as 350 mA typical (ICC3 parameter). As which allows the use of the 100 kHz version. The other a result, the VCC level slowly discharges toward 0. When solutions are: this level crosses 6.3 V typical, the controller enters a new 1. Add a series diode with pin 8 (as suggested in the startup phase by turning the current source on: VCC rises above lines) to drop the maximum input voltage toward 11.4 V and again delivers output pulses at the down to 222 V ((2 350)/pi) and thus dissipate UVLOH crossing point. If the fault condition has been less than 400 mW removed before UVLOL approaches, then the IC continues 2. Implement a self−supply through an auxiliary its normal operation. Otherwise, a new fault cycle takes winding to permanently disconnect the self−supply. place. Figure 20 shows the evolution of the signals in SOIC−8 package offers a worse R presence of a fault. qJ−A compared to that of the DIP8 package: 178°C/W. Again, adding some copper area around the PCB footprint will help decrease this number: 12 mm x 12 mm to drop RqJ−A down to 100° C/W with 35 m copper thickness (1 oz.) or 6.5 mm x 6.5 mm with 70 m copper thickness (2 oz.). One can see, we do not recommend using the SOIC package for the 100 kHz version with DSS active as the IC may not be able to sustain the power (except if you have the adequate place on your PCB). However, using the solution of the series diode or the self−supply through the auxiliary winding does not cause any problem with this frequency version. These options are thoroughly described in the AND8023/D.
www.onsemi.com 9
NCP1200 Power Dissipation Overload Operation
The NCP1200 is directly supplied from the DC rail In applications where the output current is purposely not through the internal DSS circuitry. The current flowing controlled (e.g. wall adapters delivering raw DC level), it is through the DSS is therefore the direct image of the interesting to implement a true short−circuit protection. A NCP1200 current consumption. The total power dissipation short−circuit actually forces the output voltage to be at a low can be evaluated using: (V level, preventing a bias current to circulate in the HVDC * 11 V) @ ICC2. If we operate the device on a 250 VAC rail, the maximum rectified optocoupler LED. As a result, the FB pin level is pulled up voltage can go up to 350 VDC. As a result, the worse case to 4.1 V, as internally imposed by the IC. The peak current dissipation occurs on the 100 kHz version which will setpoint goes to the maximum and the supply delivers a dissipate 340
.
1.8 mA@Tj = −25° C = 612 mW (however rather high power with all the associated effects. Please note this 1.8 mA number will drop at higher operating that this can also happen in case of feedback loss, e.g. a temperatures). Please note that in the above example, ICC2 broken optocoupler. To account for this situation, the is based on a 1 nF capacitor loading pin 5. As seen before, NCP1200 hosts a dedicated overload detection circuitry. ICC2 will depend on your MOSFET’s Qg: ICC2 = ICC1 + Fsw Once activated, this circuitry imposes to deliver pulses in a x Qg. Final calculations shall thus account for the total burst manner with a low duty cycle. The system recovers gate−charge Qg your MOSFET will exhibit. A DIP8 when the fault condition disappears. package offers a junction−to−ambient thermal resistance During the startup phase, the peak current is pushed to the of RqJ−A 100° C/W. The maximum power dissipation can maximum until the output voltage reaches its target and the thus be computed knowing the maximum operating feedback loop takes over. This period of time depends on ambient temperature (e.g. 70° C) together with the normal output load conditions and the maximum peak maximum allowable junction temperature (125° C): current allowed by the system. The time−out used by this IC T works with the VCC decoupling capacitor: as soon as the Pmax + Jmax * TAmax = 550 mW. As we can see, we do not R V RqJ*A CC decreases from the VCCOFF level (typically 11.4 V) the reach the worse consumption budget imposed by the 100 device internally watches for an overload current situation. kHz version. Two solutions exist to cure this trouble. The If this condition is still present when VCCON is reached, the first one consists in adding some copper area around the controller stops the driving pulses, prevents the self−supply NCP1200 DIP8 footprint. By adding a min−pad area of 80 current source to restart and puts all the circuitry in standby, mm2 of 35 m copper (1 oz.) RqJ−A drops to about 75° C/W consuming as little as 350 mA typical (ICC3 parameter). As which allows the use of the 100 kHz version. The other a result, the VCC level slowly discharges toward 0. When solutions are: this level crosses 6.3 V typical, the controller enters a new 1. Add a series diode with pin 8 (as suggested in the startup phase by turning the current source on: VCC rises above lines) to drop the maximum input voltage toward 11.4 V and again delivers output pulses at the down to 222 V ((2 350)/pi) and thus dissipate UVLOH crossing point. If the fault condition has been less than 400 mW removed before UVLOL approaches, then the IC continues 2. Implement a self−supply through an auxiliary its normal operation. Otherwise, a new fault cycle takes winding to permanently disconnect the self−supply. place. Figure 20 shows the evolution of the signals in SOIC−8 package offers a worse R presence of a fault. qJ−A compared to that of the DIP8 package: 178°C/W. Again, adding some copper area around the PCB footprint will help decrease this number: 12 mm x 12 mm to drop RqJ−A down to 100° C/W with 35 m copper thickness (1 oz.) or 6.5 mm x 6.5 mm with 70 m copper thickness (2 oz.). One can see, we do not recommend using the SOIC package for the 100 kHz version with DSS active as the IC may not be able to sustain the power (except if you have the adequate place on your PCB). However, using the solution of the series diode or the self−supply through the auxiliary winding does not cause any problem with this frequency version. These options are thoroughly described in the AND8023/D.
www.onsemi.com 9
