Datasheet MCP6041, MCP6042, MCP6043, MCP6044 (Microchip) - 10
| Manufacturer | Microchip |
| Description | Оperational amplifier (op amp) has a gain bandwidth product of 14 kHz with a low typical operating current of 600 nA and an offset voltage that is less than 3 mV |
| Pages / Page | 40 / 10 — MCP6041/2/3/4. Note:. 5.0. 4.5. DD = 5.0V. G = +1 V/V. G = -1 V/V. 4.0. L … |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
MCP6041/2/3/4. Note:. 5.0. 4.5. DD = 5.0V. G = +1 V/V. G = -1 V/V. 4.0. L = 50 kΩ. (V 3.5. 3.0. age. ltag. o 2.5. V 2.0. 2.0. ut V. p 1.5. tp 1.5. Out 1.0
Model Line for this Datasheet
Text Version of Document
MCP6041/2/3/4 Note:
Unless otherwise indicated, T A = +25°C, VDD = +1.4V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.
5.0 5.0 V V 4.5 DD = 5.0V DD = 5.0V G = +1 V/V 4.5 G = -1 V/V 4.0 R R ) L = 50 kΩ 4.0 ) L = 50 kΩ (V 3.5 (V 3.5 e 3.0 age 3.0 lt ltag o 2.5 o 2.5 V 2.0 ut 2.0 ut V p 1.5 tp 1.5 Out 1.0 Ou 1.0 0.5 0.5 0.0 0.0 0 1 2 3 Ti 4 me ( 5 1 ms 6 /div) 7 8 9 10 0 1 2 3 Ti 4 me ( 5 1 ms 6 /div) 7 8 9 10 FIGURE 2-31:
Large Signal Non-inverting
FIGURE 2-34:
Large Signal Inverting Pulse Pulse Response. Response.
) 7.5 5.0 3.0 ) (V V 5.0 V VOUT Active DD = 5.0V e 4.5 t ( 2.5 2.5 CS 4.0 ) u ltag tp o 0.0 3.5 (V 2.0 V -2.5 Ou S VDD = 5.0V 3.0 h 1.5 CS CS C ltage -5.0 2.5 o itc High-to-Low Low-to-High w -7.5 Output On 2.0 t V 1.0 S S -10.0 1.5 tpu V C 0.5 OUT Hysteresis -12.5 1.0 Ou al -15.0 0.5 0.0 High-Z High-Z tern VOUT High-Z -17.5 0.0 In -0.5 -20.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1 2 3 Ti 4 me 5 (1 6 ms/div7 ) 8 9 10 CS Input Voltage (V) FIGURE 2-32:
Chip Select (CS) to
FIGURE 2-35:
Chip Select (CS) Hysteresis Amplifier Output Response Time (MCP6043 (MCP6043 only). only).
1.E-02 10m )1.E-03 1m 1.E 1 -04 00µ 1.E itude (A -05 10µ n1.E-06 1µ 1.E 1 -07 00n 1.E-08 10n 1.E rrent Mag +125°C u -09 1n +85°C 1.E C t 1 -10 00p +25°C 1.E-11 10p -40°C Inpu1.E-12 1p -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) FIGURE 2-33:
Input Current vs. Input Voltage (below VSS). DS21669D-page 10 2001-2013 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6043 only). 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift with TA = -40°C to +85°C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-4: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V. FIGURE 2-5: Input Offset Voltage Drift with TA = +25°C to +125°C and VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: The MCP6041/2/3/4 family shows no phase reversal. FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel-to-Channel Separation vs. Frequency (MCP6042 and MCP6044 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-26: Slew Rate vs. Ambient Temperature. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Large Signal Non-inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6043 only). FIGURE 2-33: Input Current vs. Input Voltage (below VSS). FIGURE 2-34: Large Signal Inverting Pulse Response. FIGURE 2-35: Chip Select (CS) Hysteresis (MCP6043 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Capacitive Loads FIGURE 4-3: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.5 MCP6043 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-7: High-Side Battery Current Sensor. FIGURE 4-8: Two Op Amp Instrumentation Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service
Unless otherwise indicated, T A = +25°C, VDD = +1.4V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.
5.0 5.0 V V 4.5 DD = 5.0V DD = 5.0V G = +1 V/V 4.5 G = -1 V/V 4.0 R R ) L = 50 kΩ 4.0 ) L = 50 kΩ (V 3.5 (V 3.5 e 3.0 age 3.0 lt ltag o 2.5 o 2.5 V 2.0 ut 2.0 ut V p 1.5 tp 1.5 Out 1.0 Ou 1.0 0.5 0.5 0.0 0.0 0 1 2 3 Ti 4 me ( 5 1 ms 6 /div) 7 8 9 10 0 1 2 3 Ti 4 me ( 5 1 ms 6 /div) 7 8 9 10 FIGURE 2-31:
Large Signal Non-inverting
FIGURE 2-34:
Large Signal Inverting Pulse Pulse Response. Response.
) 7.5 5.0 3.0 ) (V V 5.0 V VOUT Active DD = 5.0V e 4.5 t ( 2.5 2.5 CS 4.0 ) u ltag tp o 0.0 3.5 (V 2.0 V -2.5 Ou S VDD = 5.0V 3.0 h 1.5 CS CS C ltage -5.0 2.5 o itc High-to-Low Low-to-High w -7.5 Output On 2.0 t V 1.0 S S -10.0 1.5 tpu V C 0.5 OUT Hysteresis -12.5 1.0 Ou al -15.0 0.5 0.0 High-Z High-Z tern VOUT High-Z -17.5 0.0 In -0.5 -20.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1 2 3 Ti 4 me 5 (1 6 ms/div7 ) 8 9 10 CS Input Voltage (V) FIGURE 2-32:
Chip Select (CS) to
FIGURE 2-35:
Chip Select (CS) Hysteresis Amplifier Output Response Time (MCP6043 (MCP6043 only). only).
1.E-02 10m )1.E-03 1m 1.E 1 -04 00µ 1.E itude (A -05 10µ n1.E-06 1µ 1.E 1 -07 00n 1.E-08 10n 1.E rrent Mag +125°C u -09 1n +85°C 1.E C t 1 -10 00p +25°C 1.E-11 10p -40°C Inpu1.E-12 1p -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) FIGURE 2-33:
Input Current vs. Input Voltage (below VSS). DS21669D-page 10 2001-2013 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6043 only). 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift with TA = -40°C to +85°C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-4: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V. FIGURE 2-5: Input Offset Voltage Drift with TA = +25°C to +125°C and VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: The MCP6041/2/3/4 family shows no phase reversal. FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel-to-Channel Separation vs. Frequency (MCP6042 and MCP6044 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-26: Slew Rate vs. Ambient Temperature. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Large Signal Non-inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6043 only). FIGURE 2-33: Input Current vs. Input Voltage (below VSS). FIGURE 2-34: Large Signal Inverting Pulse Response. FIGURE 2-35: Chip Select (CS) Hysteresis (MCP6043 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Capacitive Loads FIGURE 4-3: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.5 MCP6043 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-7: High-Side Battery Current Sensor. FIGURE 4-8: Two Op Amp Instrumentation Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service
