Datasheet MCP6271, MCP6271R, MCP6272, MCP6273, MCP6274, MCP6275 (Microchip) - 7

MCP6271/1R/2/3/4/5 Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
0.00 e 0.50 e g -0.05 Typical lower (VCM – VSS) limit g 0.45 -0.10 0.40 VDD = 5.5V Volta Volta t -0.15 (V) t 0.35 it -0.20 V it (V) DD = 2.0V 0.30 -0.25 0.25 de Inpu Lim de Inpu Lim -0.30 0.20 nge nge VDD = 2.0V -0.35 0.15 Ra V Ra DD = 5.5V -0.40 0.10 mmon Mo -0.45 mmon Mo o 0.05 o Typical upper (VCM – VDD) limit C -0.50 C 0.00 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-7:
Common Mode Input
FIGURE 2-10:
Common Mode Input Voltage Range Lower Limit vs. Temperature. Voltage Range Upper Limit vs. Temperature.
300 V 10,000 CM = VSS 250 V) V Representative Part ts CM = VDD (µ V 200 e DD = 5.5V rren 1,000 ag 150 lt Cu 100 ) t Vo fset A 100 Input Bias Current e (p 50 ffs , Of t O 0 ias u V 10 DD = 2.0V VDD = 5.5V p t B Input Offset Current -50 In u p -100 In 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 45 55 65 75 85 95 105 115 125 Output Voltage (V) Ambient Temperature (°C) FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
Input Bias, Input Offset Output Voltage. Currents vs. Temperature.
110 120 100 CMRR 110 ) 90 B) (d 80 (dB 100 CMRR R R 70 RR S M 90 60 PSRR– , P PSRR+ R, C PSRR 50 80 RR R (V S CM = VSS) 40 CM P 70 30 20 60 1.E+ 1 00 1.E+0 10 1 1.E+ 10 02 0 1.E+ 1 03 k 1.E+04 10k 1.E+ 10 05 0k 1.E+06 1M -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-9:
CMRR, PSRR vs.
FIGURE 2-12:
CMRR, PSRR vs. Frequency. Temperature. © 2008 Microchip Technology Inc. DS21810F-page 7 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6273 and MCP6275. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Bias Current at TA = +85˚C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V. FIGURE 2-4: Input Offset Voltage Drift. FIGURE 2-5: Input Bias Current at TA = +125˚C. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 5.5V. FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs. Temperature. FIGURE 2-8: Input Offset Voltage vs. Output Voltage. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: Common Mode Input Voltage Range Upper Limit vs. Temperature. FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature. FIGURE 2-12: CMRR, PSRR vs. Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +85˚C. FIGURE 2-14: Quiescent Current vs. Supply Voltage. FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125˚C. FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature. FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-20: Input Noise Voltage Density vs. Frequency. FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage. FIGURE 2-22: Slew Rate vs. Temperature. FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage, with f = 1 kHz. FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274). FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only). FIGURE 2-26: Large Signal Non-inverting Pulse Response. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only). FIGURE 2-29: Large Signal Inverting Pulse Response. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only). FIGURE 2-32: Input Current vs. Input Voltage. FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only). FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 MCP6275’s VOUTA/VINB+ Pin 3.4 Chip Select Digital Input 3.5 Power Supply Pins 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.4 MCP6273/5 Chip Select 4.5 Cascaded Dual Op Amps (MCP6275) FIGURE 4-5: Cascaded Gain Amplifier. 4.6 Unused Amplifiers FIGURE 4-6: Unused Op Amps. 4.7 Supply Bypass 4.8 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-8: Active Full-wave Rectifier. FIGURE 4-9: Non-Inverting Integrator. FIGURE 4-10: Isolating the Load with a Buffer. FIGURE 4-11: Cascaded Gain Circuit Configuration. FIGURE 4-12: Difference Amplifier Circuit. FIGURE 4-13: Integrator Circuit with Active Compensation. FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair. FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select. 5.0 Design Tools 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information