Datasheet AD7771 (Analog Devices)

8-Channel, 24-Bit, Simultaneous Sampling ADC Data Sheet AD7771 FEATURES
voltage from 1 V up to 3.6 V. The analog inputs accept unipolar
8-channel, 24-bit simultaneous sampling ADC
(0 V to VREF) or true bipolar (±VREF/2 V) analog input signals with
Single-ended or true differential inputs
3.3 V or ±1.65 V analog supply voltages, respectively. The analog
PGA per channel (gains of 1, 2, 4, and 8)
inputs can be configured to accept true differential or single-ended
Low dc input current
signals to match different sensor output configurations.
±4 nA (differential)/±8 nA (single-ended)
Each channel contains an ADC modulator and a sinc3/sinc5, low
Up to 128 kSPS ODR per channel
latency digital filter. A sample rate converter (SRC) is provided to
Programmable ODRs and bandwidth
al ow fine resolution control over the AD7771 output data rate
SRC for coherent sampling
(ODR). This control can be used in applications where the ODR
Sampling rate resolution up to 15.2 × 10−6 SPS
resolution is required to maintain coherency with 0.01 Hz
Low latency sinc3 and sinc5 filter paths
changes in the line frequency. The SRC is programmable through
Adjustable phase synchronization
the serial port interface (SPI). The AD7771 implements two
Internal 2.5 V reference
different interfaces: a data output interface and SPI control
Two power modes
interface. The ADC data output interface is dedicated to trans-
High resolution mode
mitting the ADC conversion results from the AD7771 to the
Low power mode
processor. The SPI writes to and reads from the AD7771
Optimizes power dissipation and performance
configuration registers and for the control and reading of data
Low resolution SAR ADC for system and chip diagnostics
from the successive approximation register (SAR) ADC. The SPI
Power supply
can also be configured to output the Σ-Δ conversion data.
Bipolar (±1.65 V) or unipolar (3.3 V) supplies Digital I/O supply: 1.8 V to 3.6 V
The AD7771 includes a 12-bit SAR ADC. This ADC can be used
Performance temperature range: −40°C to +105°C
for AD7771 diagnostics without having to decommission one of
Functional temperature range: −40°C to +125°C
the Σ-Δ ADC channels dedicated to system measurement func-
Performance
tions. With the use of an external multiplexer, which can be
Combined ac and dc performance
control ed through the three general-purpose input/output pins
107 dB SNR/dynamic range at 32 kSPS in high resolution
(GPIOs), and signal conditioning, the SAR ADC can validate
mode (sinc5)
the Σ-Δ ADC measurements in applications where functional
−109 dB THD
safety is required. In addition, the AD7771 SAR ADC includes
±8 ppm of FSR INL
an internal multiplexer to sense internal nodes.
±15 µV offset error
The AD7771 contains a 2.5 V reference and reference buffer. The
±0.1% FS gain error
reference has a typical temperature coefficient of ±10 ppm/°C.
±10 ppm/°C typical temperature coefficient
The AD7771 offers two modes of operation: high resolution
APPLICATIONS
mode and low power mode. High resolution mode provides a
Power quality and measurement applications
higher dynamic range while consuming 16.6 mW per channel;
General-purpose data acquisition
low power mode consumes only 5.25 mW per channel at a
Electroencephalography (EEG)
reduced dynamic range specification.
Industrial process control
The specified operating temperature range is −40°C to +105°C,
GENERAL DESCRIPTION
although the device is operational up to +125°C. The AD77711 is an 8-channel, simultaneous sampling analog-to- Note that throughout this data sheet, certain terms are used to digital converter (ADC). Eight full Σ-Δ ADCs are on-chip. The refer to either the multifunction pins or a range of pins. The AD7771 provides an ultralow input current to al ow direct sensor multifunction pins, such as DCLK0/SDO, are referred to either connection. Each input channel has a programmable gain stage by the entire pin name or by a single function of the pin, for al owing gains of 1, 2, 4, and 8 to map lower amplitude sensor example, DCLK0, when only that function is relevant. In the outputs into the ful -scale ADC input range, maximizing the case of ranges of pins, AVSSx refers to the following pins: dynamic range of the signal chain. The AD7771 accepts a V AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. REF 1 This product is protected by at least U.S. Patent No. 9.432,043.
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DOUTx TIMING CHARACTERISTISTICS SPI TIMING CHARACTERISTISTICS SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS SAR ADC TIMING CHARACTERISTISTICS GPIO SRC UPDATE TIMING CHARACTERISTISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUTS TRANSFER FUNCTION CORE SIGNAL CHAIN CAPACITIVE PGA INTERNAL REFERENCE AND REFERENCE BUFFERS INTEGRATED LDOs CLOCKING AND SAMPLING DIGITAL RESET AND SYNCHRONIZATION PINS DIGITAL FILTERING SHUTDOWN MODE CONTROLLING THE AD7771 PIN CONTROL MODE SPI CONTROL Functionality Available in SPI Control Mode Offset and Gain Correction SPI Control Functionality Global Control Functions Per Channel Functions Phase Adjustment PGA Gain Decimation GPIOx Pins Σ-Δ Reference Configuration Power Modes Sinc3 and Sinc5 Filters LDO Bypassing DIGITAL SPI SPI CRC—Checksum Protection (SPI Control Mode) SPI Read/Write Register Mode (SPI Control Mode) SPI SAR Diagnostic Mode (SPI Control Mode) Σ-Δ Data, ADC Mode SPI Software Reset RMS NOISE AND RESOLUTION HIGH RESOLUTION MODE LOW POWER MODE DIAGNOSTICS AND MONITORING SELF DIAGNOSTICS ERROR General Errors MCLK Switch Error (SPI Control Mode) Reset Detection Internal LDO Status ROM and Memory Map CRC Σ-Δ ADC Errors Reference Detect (SPI Control Mode) Overvoltage and Undervoltage Events Modulator Saturation Filter Saturation Output Saturation SPI Transmission Errors (SPI Control Mode) CRC Checksum Error SCLK Counter Invalid Read Invalid Write MONITORING USING THE AD7771 SAR ADC(SPI CONTROL MODE) Temperature Sensor Σ-Δ ADC DIAGNOSTICS (SPI CONTROL MODE) Σ-∆ OUTPUT DATA ADC CONVERSION OUTPUT—HEADER AND DATA CRC Header Error Header (SPI Control Mode) SAMPLE RATE CONVERTER (SRC) (SPI CONTROL MODE) SRC Bandwidth SRC Group Delay Settling Time DATA OUTPUT INTERFACE DOUT3 to DOUT0 Data Interface Standalone Mode Daisy-Chain Mode Minimum DCLKx Frequency SPI CALCULATING THE CRC CHECKSUM Σ-Δ CRC Checksum SPI Control Mode Checksum REGISTER SUMMARY REGISTER DETAILS CHANNEL 0 CONFIGURATION REGISTER CHANNEL 1 CONFIGURATION REGISTER CHANNEL 2 CONFIGURATION REGISTER CHANNEL 3 CONFIGURATION REGISTER CHANNEL 4 CONFIGURATION REGISTER CHANNEL 5 CONFIGURATION REGISTER CHANNEL 6 CONFIGURATION REGISTER CHANNEL 7 CONFIGURATION REGISTER DISABLE CLOCKS TO ADC CHANNEL REGISTER CHANNEL 0 SYNC OFFSET REGISTER CHANNEL 1 SYNC OFFSET REGISTER CHANNEL 2 SYNC OFFSET REGISTER CHANNEL 3 SYNC OFFSET REGISTER CHANNEL 4 SYNC OFFSET REGISTER CHANNEL 5 SYNC OFFSET REGISTER CHANNEL 6 SYNC OFFSET REGISTER CHANNEL 7 SYNC OFFSET REGISTER GENERAL USER CONFIGURATION 1 REGISTER GENERAL USER CONFIGURATION 2 REGISTER GENERAL USER CONFIGURATION 3 REGISTER DATA OUTPUT FORMAT REGISTER MAIN ADC METER AND REFERENCE MUX CONTROL REGISTER GLOBAL DIAGNOSTICS MUX REGISTER GPIO CONFIGURATION REGISTER GPIO DATA REGISTER BUFFER CONFIGURATION 1 REGISTER BUFFER CONFIGURATION 2 REGISTER CHANNEL 0 OFFSET UPPER BYTE REGISTER CHANNEL 0 OFFSET MIDDLE BYTE REGISTER CHANNEL 0 OFFSET LOWER BYTE REGISTER CHANNEL 0 GAIN UPPER BYTE REGISTER CHANNEL 0 GAIN MIDDLE BYTE REGISTER CHANNEL 0 GAIN LOWER BYTE REGISTER CHANNEL 1 OFFSET UPPER BYTE REGISTER CHANNEL 1 OFFSET MIDDLE BYTE REGISTER CHANNEL 1 OFFSET LOWER BYTE REGISTER CHANNEL 1 GAIN UPPER BYTE REGISTER CHANNEL 1 GAIN MIDDLE BYTE REGISTER CHANNEL 1 GAIN LOWER BYTE REGISTER CHANNEL 2 OFFSET UPPER BYTE REGISTER CHANNEL 2 OFFSET MIDDLE BYTE REGISTER CHANNEL 2 OFFSET LOWER BYTE REGISTER CHANNEL 2 GAIN UPPER BYTE REGISTER CHANNEL 2 GAIN MIDDLE BYTE REGISTER CHANNEL 2 GAIN LOWER BYTE REGISTER CHANNEL 3 OFFSET UPPER BYTE REGISTER CHANNEL 3 OFFSET MIDDLE BYTE REGISTER CHANNEL 3 OFFSET LOWER BYTE REGISTER CHANNEL 3 GAIN UPPER BYTE REGISTER CHANNEL 3 GAIN MIDDLE BYTE REGISTER CHANNEL 3 GAIN LOWER BYTE REGISTER CHANNEL 4 OFFSET UPPER BYTE REGISTER CHANNEL 4 OFFSET MIDDLE BYTE REGISTER CHANNEL 4 OFFSET LOWER BYTE REGISTER CHANNEL 4 GAIN UPPER BYTE REGISTER CHANNEL 4 GAIN MIDDLE BYTE REGISTER CHANNEL 4 GAIN LOWER BYTE REGISTER CHANNEL 5 OFFSET UPPER BYTE REGISTER CHANNEL 5 OFFSET MIDDLE BYTE REGISTER CHANNEL 5 OFFSET LOWER BYTE REGISTER CHANNEL 5 GAIN UPPER BYTE REGISTER CHANNEL 5 GAIN MIDDLE BYTE REGISTER CHANNEL 5 GAIN LOWER BYTE REGISTER CHANNEL 6 OFFSET UPPER BYTE REGISTER CHANNEL 6 OFFSET MIDDLE BYTE REGISTER CHANNEL 6 OFFSET LOWER BYTE REGISTER CHANNEL 6 GAIN UPPER BYTE REGISTER CHANNEL 6 GAIN MIDDLE BYTE REGISTER CHANNEL 6 GAIN LOWER BYTE REGISTER CHANNEL 7 OFFSET UPPER BYTE REGISTER CHANNEL 7 OFFSET MIDDLE BYTE REGISTER CHANNEL 7 OFFSET LOWER BYTE REGISTER CHANNEL 7 GAIN UPPER BYTE REGISTER CHANNEL 7 GAIN MIDDLE BYTE REGISTER CHANNEL 7 GAIN LOWER BYTE REGISTER CHANNEL 0 STATUS REGISTER CHANNEL 1 STATUS REGISTER CHANNEL 2 STATUS REGISTER CHANNEL 3 STATUS REGISTER CHANNEL 4 STATUS REGISTER CHANNEL 5 STATUS REGISTER CHANNEL 6 STATUS REGISTER CHANNEL 7 STATUS REGISTER CHANNEL 0/CHANNEL 1 DSP ERRORS REGISTER CHANNEL 2/CHANNEL 3 DSP ERRORS REGISTER CHANNEL 4/CHANNEL 5 DSP ERRORS REGISTER CHANNEL 6/CHANNEL 7 DSP ERRORS REGISTER CHANNEL 0 TO CHANNEL 7 ERROR REGISTER ENABLE REGISTER GENERAL ERRORS REGISTER 1 GENERAL ERRORS REGISTER 1 ENABLE GENERAL ERRORS REGISTER 2 GENERAL ERRORS REGISTER 2 ENABLE ERROR STATUS REGISTER 1 ERROR STATUS REGISTER 2 ERROR STATUS REGISTER 3 DECIMATION RATE (N) MSB REGISTER DECIMATION RATE (N) LSB REGISTER DECIMATION RATE (IF) MSB REGISTER DECIMATION RATE (IF) LSB REGISTER SRC LOAD SOURCE AND LOAD UPDATE REGISTER OUTLINE DIMENSIONS ORDERING GUIDE