Datasheet ADA4622-1, ADA4622-2, ADA4622-4 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 30 V, 8 MHz, Low Bias Current, Single-Supply, RRO, Precision Quad Op Amp |
| Pages / Page | 37 / 9 — Data Sheet. ADA4622-1/. ADA4622-2/. ADA4622-4. ABSOLUTE MAXIMUM RATINGS. … |
| Revision | E |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
Data Sheet. ADA4622-1/. ADA4622-2/. ADA4622-4. ABSOLUTE MAXIMUM RATINGS. THERMAL RESISTANCE. Table 4. Parameter. Rating
Text Version of Document
Data Sheet ADA4622-1/ ADA4622-2/ ADA4622-4 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Rating
Thermal performance is directly linked to printed circuit board Supply Voltage 36 V (PCB) design and operating environment. Close attention to Input Voltage (V−) − 0.3 V to PCB thermal design is required. (V+) + 0.2 V
Table 5. Thermal Resistance1, 2
Differential Input Voltage 36 V
Package Type θ 3 Unit
Storage Temperature Range −65°C to +150°C
JA θJC
8-Lead SOIC Operating Temperature Range −40°C to +125°C 1-Layer JEDEC Board N/A 63 °C/W Junction Temperature Range −65°C to +150°C 2-Layer JEDEC Board 120 N/A °C/W Lead Temperature, Soldering (10 sec) 300°C 8-Lead MSOP ESD Rating, Human Body Model (HBM) 4 kV 1-Layer JEDEC Board N/A 115 °C/W Stresses at or above those listed under Absolute Maximum 2-Layer JEDEC Board 185 N/A °C/W Ratings may cause permanent damage to the product. This is a 8-Lead LFCSP stress rating only; functional operation of the product at these 1-Layer JEDEC Board N/A 63 °C/W or any other conditions above those indicated in the operational 2-Layer JEDEC Board 145 N/A °C/W section of this specification is not implied. Operation beyond 2-Layer JEDEC Board with 2 × 2 Vias 55 N/A °C/W the maximum operating conditions for extended periods may 5-Lead SOT-23 affect product reliability. 1-Layer JEDEC Board N/A 82 °C/W 2-Layer JEDEC Board 339 N/A °C/W 14-Lead SOIC 1-Layer JEDEC Board N/A 42 °C/W 2-Layer JEDEC Board 72 N/A °C/W 16-Lead, 4 × 4 mm LFCSP 1-Layer JEDEC Board N/A 2.2 °C/W 2-Layer JEDEC Board 48 N/A °C/W 1 Thermal impedance simulated values are based on a JEDEC thermal test board. See JEDEC JESD51. 2 N/A means not applicable. 3 For θJC test, 100 μm thermal interface material (TIM) is used. TIM is assumed to have 3.6 W/mK
ESD CAUTION
Rev. C | Page 9 of 37 Document Outline FEATURES APPLICATIONS PIN CONFIGURATION GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS, VSY = ±15 V ELECTRICAL CHARACTERISTICS, VSY = ±5 V ELECTRICAL CHARACTERISTICS, VSY = 5 V ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT CHARACTERISTICS Input Overvoltage Protection EMI Rejection Ratio OUTPUT CHARACTERISTICS Capacitive Load Drive Capability SHUTDOWN OPERATION APPLICATIONS INFORMATION RECOMMENDED POWER SOLUTION MAXIMUM POWER DISSIPATION SECOND-ORDER LOW-PASS FILTER WIDEBAND PHOTODIODE PREAMPLIFIER PEAK DETECTOR MULTIPLEXING INPUTS FULL WAVE RECTIFIER OUTLINE DIMENSIONS ORDERING GUIDE
Thermal performance is directly linked to printed circuit board Supply Voltage 36 V (PCB) design and operating environment. Close attention to Input Voltage (V−) − 0.3 V to PCB thermal design is required. (V+) + 0.2 V
Table 5. Thermal Resistance1, 2
Differential Input Voltage 36 V
Package Type θ 3 Unit
Storage Temperature Range −65°C to +150°C
JA θJC
8-Lead SOIC Operating Temperature Range −40°C to +125°C 1-Layer JEDEC Board N/A 63 °C/W Junction Temperature Range −65°C to +150°C 2-Layer JEDEC Board 120 N/A °C/W Lead Temperature, Soldering (10 sec) 300°C 8-Lead MSOP ESD Rating, Human Body Model (HBM) 4 kV 1-Layer JEDEC Board N/A 115 °C/W Stresses at or above those listed under Absolute Maximum 2-Layer JEDEC Board 185 N/A °C/W Ratings may cause permanent damage to the product. This is a 8-Lead LFCSP stress rating only; functional operation of the product at these 1-Layer JEDEC Board N/A 63 °C/W or any other conditions above those indicated in the operational 2-Layer JEDEC Board 145 N/A °C/W section of this specification is not implied. Operation beyond 2-Layer JEDEC Board with 2 × 2 Vias 55 N/A °C/W the maximum operating conditions for extended periods may 5-Lead SOT-23 affect product reliability. 1-Layer JEDEC Board N/A 82 °C/W 2-Layer JEDEC Board 339 N/A °C/W 14-Lead SOIC 1-Layer JEDEC Board N/A 42 °C/W 2-Layer JEDEC Board 72 N/A °C/W 16-Lead, 4 × 4 mm LFCSP 1-Layer JEDEC Board N/A 2.2 °C/W 2-Layer JEDEC Board 48 N/A °C/W 1 Thermal impedance simulated values are based on a JEDEC thermal test board. See JEDEC JESD51. 2 N/A means not applicable. 3 For θJC test, 100 μm thermal interface material (TIM) is used. TIM is assumed to have 3.6 W/mK
ESD CAUTION
Rev. C | Page 9 of 37 Document Outline FEATURES APPLICATIONS PIN CONFIGURATION GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS, VSY = ±15 V ELECTRICAL CHARACTERISTICS, VSY = ±5 V ELECTRICAL CHARACTERISTICS, VSY = 5 V ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT CHARACTERISTICS Input Overvoltage Protection EMI Rejection Ratio OUTPUT CHARACTERISTICS Capacitive Load Drive Capability SHUTDOWN OPERATION APPLICATIONS INFORMATION RECOMMENDED POWER SOLUTION MAXIMUM POWER DISSIPATION SECOND-ORDER LOW-PASS FILTER WIDEBAND PHOTODIODE PREAMPLIFIER PEAK DETECTOR MULTIPLEXING INPUTS FULL WAVE RECTIFIER OUTLINE DIMENSIONS ORDERING GUIDE
