Datasheet LTC1289 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 3 Volt Single Chip 12-Bit Data Acquisition System |
| Pages / Page | 28 / 7 — PI FU CTIO S. CH0 – CH7 (Pins 1 – 8):. CS (Pin 15):. COM (Pin 9):. DOUT … |
| File Format / Size | PDF / 685 Kb |
| Document Language | English |
PI FU CTIO S. CH0 – CH7 (Pins 1 – 8):. CS (Pin 15):. COM (Pin 9):. DOUT (Pin 16):. DIN (Pin 17):. DGND (Pin 10):. SCLK (Pin 18):
Model Line for this Datasheet
Text Version of Document
LTC1289
U U U PI FU CTIO S CH0 – CH7 (Pins 1 – 8):
Analog Inputs. The analog in-
CS (Pin 15):
Chip Select Input. A logic low on this input puts must be free of noise with respect to AGND. enables data transfer.
COM (Pin 9):
Common. The common pin defines the zero
DOUT (Pin 16):
Digital Data Output. The A/D conversion reference point for all single-ended inputs. It must be free result is shifted out of this output. of noise and is usually tied to the analog ground plane.
DIN (Pin 17):
Digital Input. The A/D configuration word is
DGND (Pin 10):
Digital Ground. This is the ground for the shifted into this input. internal logic. Tie to the ground plane.
SCLK (Pin 18):
Shift Clock. This clock synchronizes the
AGND (Pin 11):
Analog Ground. AGND should be tied di- serial data transfer. rectly to the analog ground plane.
ACLK (Pin 19):
A/D Conversion Clock. This clock con-
V– (Pin 12):
Negative Supply. Tie V– to the most negative trols the A/D conversion process. potential in the circuit. (Ground in single supply applica- tions.)
VCC (Pin 20):
Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog
REF–, REF+ (Pins 13,14)
Reference Inputs. The reference ground plane. inputs must be kept free of noise with respect to AGND.
BLOCK DIAGRAM
18 20 SCLK VCC INPUT 17 OUTPUT 16 D SHIFT SHIFT D IN OUT REGISTER REGISTER 1 CH0 SAMPLE 2 CH1 AND 3 HOLD CH2 COMP 4 CH3 ANALOG 5 12-BIT INPUT MUX CH4 SAR 6 CH5 12-BIT 7 CH6 CAPACITIVE 8 DAC CH7 9 COM 19 ACLK CONTROL 15 10 11 12 13 14 AND CS TIMING DGND AGND V– REF– REF+ LTC1289 BD 1289fb 7
U U U PI FU CTIO S CH0 – CH7 (Pins 1 – 8):
Analog Inputs. The analog in-
CS (Pin 15):
Chip Select Input. A logic low on this input puts must be free of noise with respect to AGND. enables data transfer.
COM (Pin 9):
Common. The common pin defines the zero
DOUT (Pin 16):
Digital Data Output. The A/D conversion reference point for all single-ended inputs. It must be free result is shifted out of this output. of noise and is usually tied to the analog ground plane.
DIN (Pin 17):
Digital Input. The A/D configuration word is
DGND (Pin 10):
Digital Ground. This is the ground for the shifted into this input. internal logic. Tie to the ground plane.
SCLK (Pin 18):
Shift Clock. This clock synchronizes the
AGND (Pin 11):
Analog Ground. AGND should be tied di- serial data transfer. rectly to the analog ground plane.
ACLK (Pin 19):
A/D Conversion Clock. This clock con-
V– (Pin 12):
Negative Supply. Tie V– to the most negative trols the A/D conversion process. potential in the circuit. (Ground in single supply applica- tions.)
VCC (Pin 20):
Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog
REF–, REF+ (Pins 13,14)
Reference Inputs. The reference ground plane. inputs must be kept free of noise with respect to AGND.
BLOCK DIAGRAM
18 20 SCLK VCC INPUT 17 OUTPUT 16 D SHIFT SHIFT D IN OUT REGISTER REGISTER 1 CH0 SAMPLE 2 CH1 AND 3 HOLD CH2 COMP 4 CH3 ANALOG 5 12-BIT INPUT MUX CH4 SAR 6 CH5 12-BIT 7 CH6 CAPACITIVE 8 DAC CH7 9 COM 19 ACLK CONTROL 15 10 11 12 13 14 AND CS TIMING DGND AGND V– REF– REF+ LTC1289 BD 1289fb 7
