Datasheet LTC1292, LTC1297 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Single Chip 12-Bit Data Acquisition Systems |
| Pages / Page | 24 / 6 — TYPICAL PERFOR A CE CH. ARA TERISTICS. Maximum Clock Rate vs. Maximum … |
| File Format / Size | PDF / 325 Kb |
| Document Language | English |
TYPICAL PERFOR A CE CH. ARA TERISTICS. Maximum Clock Rate vs. Maximum Filter Resistor vs. Sample-and-Hold Acquisition
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LTC1292/LTC1297
W U TYPICAL PERFOR A CE CH C ARA TERISTICS Maximum Clock Rate vs Maximum Filter Resistor vs Sample-and-Hold Acquisition Source Resistance Cycle Time Time vs Source Resistance
1.0 10k 100 VCC = 5V V V REF = 5V REF = 5V µs) V CLK = 1MHz RFILTER CC = 5V 0.8 +VIN + T ) A = 25°C Ω 1k CFILTER ≥1µF 0V TO 5V INPUT STEP +V – IN + +IN ** ( 0.6 RSOURCE – R –IN SOURCE FILTER 100 10 +VIN + 0.4 – 10 MAXIMUM R 0.2 MAXIMUM CLK FREQUENCY* (MHz) S & H AQUISITION TIME TO 0.02% ( 0 1 1 100 1k 10k 100k 10 100 1k 10k 100 1000 10000 RSOURCE– (Ω) CYCLE TIME (µs) RSOURCE+ (Ω) LTC1292/7G13 LTC1292/7 G14 LTC1292/7 G15
Input Channel Leakage Current vs Temperature Noise Error vs Reference Voltage
1000 2.25 * MAXIMUM CLK FREQUENCY REPRESENTS THE LTC1292/LTC1297 CLK FREQUENCY AT WHICH A 0.1LSB SHIFT IN 900 GUARANTEED 2.00 NOISE = 200µVP-P THE ERROR AT ANY CODE TRANSITION FROM ITS 800 1MHz VALUE IS FIRST DETECTED. 1.75 700 1.50 ** MAXIMUM RFILTER REPRESENTS THE FILTER 600 RESISTOR VALUE AT WHICH A 0.1LSB CHANGE IN 1.25 FULL SCALE ERROR FROM ITS VALUE AT 500 RFILTER = 0Ω IS FIRST DETECTED. 1.00 400 0.75 300 0.50 200 ON CHANNEL PEAK-TO-PEAK NOISE ERROR (LSB) 100 0.25 INPUT CHANNEL LEAKAGE CURRENT (nA) OFF CHANNEL 0 0 –50 –30 –10 10 30 50 70 90 110 130 0 1 2 3 4 5 AMBIENT TEMPERATURE (°C) REFERENCE VOLTAGE (V) LTC1292/7 G16 LTC1292/7 G17
U U U PI FU CTIO S CS (Pin 1):
Chip Select Input. A logic low on this input
DOUT (Pin 6):
Digital Data Output. The A/D conversion enables the LTC1292/LTC1297. Power shutdown is acti- result is shifted out of this output. vated on the LTC1297 when CS is brought high.
CLK (Pin 7):
Shift Clock. This clock synchronizes the serial
+IN, –IN (Pin 2, 3):
Analog Inputs. These inputs must be data transfer. free of noise with respect to GND.
VCC (Pin 8):
Positive Supply. This supply must be kept free
GND (Pin 4):
Analog Ground. GND should be tied directly of noise and ripple by bypassing directly to the analog to an analog ground plane. ground plane.
VREF (Pin 5):
Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. 12927fb 6
W U TYPICAL PERFOR A CE CH C ARA TERISTICS Maximum Clock Rate vs Maximum Filter Resistor vs Sample-and-Hold Acquisition Source Resistance Cycle Time Time vs Source Resistance
1.0 10k 100 VCC = 5V V V REF = 5V REF = 5V µs) V CLK = 1MHz RFILTER CC = 5V 0.8 +VIN + T ) A = 25°C Ω 1k CFILTER ≥1µF 0V TO 5V INPUT STEP +V – IN + +IN ** ( 0.6 RSOURCE – R –IN SOURCE FILTER 100 10 +VIN + 0.4 – 10 MAXIMUM R 0.2 MAXIMUM CLK FREQUENCY* (MHz) S & H AQUISITION TIME TO 0.02% ( 0 1 1 100 1k 10k 100k 10 100 1k 10k 100 1000 10000 RSOURCE– (Ω) CYCLE TIME (µs) RSOURCE+ (Ω) LTC1292/7G13 LTC1292/7 G14 LTC1292/7 G15
Input Channel Leakage Current vs Temperature Noise Error vs Reference Voltage
1000 2.25 * MAXIMUM CLK FREQUENCY REPRESENTS THE LTC1292/LTC1297 CLK FREQUENCY AT WHICH A 0.1LSB SHIFT IN 900 GUARANTEED 2.00 NOISE = 200µVP-P THE ERROR AT ANY CODE TRANSITION FROM ITS 800 1MHz VALUE IS FIRST DETECTED. 1.75 700 1.50 ** MAXIMUM RFILTER REPRESENTS THE FILTER 600 RESISTOR VALUE AT WHICH A 0.1LSB CHANGE IN 1.25 FULL SCALE ERROR FROM ITS VALUE AT 500 RFILTER = 0Ω IS FIRST DETECTED. 1.00 400 0.75 300 0.50 200 ON CHANNEL PEAK-TO-PEAK NOISE ERROR (LSB) 100 0.25 INPUT CHANNEL LEAKAGE CURRENT (nA) OFF CHANNEL 0 0 –50 –30 –10 10 30 50 70 90 110 130 0 1 2 3 4 5 AMBIENT TEMPERATURE (°C) REFERENCE VOLTAGE (V) LTC1292/7 G16 LTC1292/7 G17
U U U PI FU CTIO S CS (Pin 1):
Chip Select Input. A logic low on this input
DOUT (Pin 6):
Digital Data Output. The A/D conversion enables the LTC1292/LTC1297. Power shutdown is acti- result is shifted out of this output. vated on the LTC1297 when CS is brought high.
CLK (Pin 7):
Shift Clock. This clock synchronizes the serial
+IN, –IN (Pin 2, 3):
Analog Inputs. These inputs must be data transfer. free of noise with respect to GND.
VCC (Pin 8):
Positive Supply. This supply must be kept free
GND (Pin 4):
Analog Ground. GND should be tied directly of noise and ripple by bypassing directly to the analog to an analog ground plane. ground plane.
VREF (Pin 5):
Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. 12927fb 6
