Datasheet LTC1402 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Serial 12-Bit, 2.2Msps Sampling ADC with Shutdown |
| Pages / Page | 24 / 5 — ELECTRICAL CHARACTERISTICS. Note 12:. Note 16:. Note 13:. Note 17:. Note … |
| File Format / Size | PDF / 292 Kb |
| Document Language | English |
ELECTRICAL CHARACTERISTICS. Note 12:. Note 16:. Note 13:. Note 17:. Note 14:. Note 15:. Note 18:
Model Line for this Datasheet
Text Version of Document
LTC1402
ELECTRICAL CHARACTERISTICS Note 12:
The absolute voltage at A + – IN and AIN must be within this range.
Note 16:
The time period for acquiring the input signal is started by the
Note 13:
If less than 7.3ns is allowed, the output data will appear one 14th rising clock and it is ended by the rising edge of convert. clock cycle later. It is best for CONV to rise half a clock before SCK, when
Note 17:
The internal reference settles in 2ms after it wakes up from Sleep running the clock at rated speed. mode with one or more cycles at SCK and a 10µF capacitive load. The
Note 14:
Not the same as aperture delay. Aperture delay is smaller (2.6ns) Sleep mode resets the REFREADY bit in the DOUT sequence. The because the 0.8ns delay through the sample-and-hold is subtracted from REFREADY bit goes high again 10ms after the VREF has stopped slewing in the CONV to Hold mode delay. wake up. This ensures valid REFREADY bit operation even with higher load
Note 15:
The rising edge of SCK is guaranteed to catch the data coming capacitances at VREF. out into a storage latch.
Note 18:
The full power bandwidth is the frequency where the output code swing drops to 2828LSBs with a 4VP-P input sine wave.
W U TYPICAL PERFOR A CE CHARACTERISTICS (Bipolar Mode Plots Run with Dual
±
5V Supplies. Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = – 5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25
°
C. 5 Harmonic THD, 2nd, 3rd and ENOBs and SINAD SFDR vs Input Frequency vs Input Frequency (Bipolar) (Bipolar) SNR vs Input Frequency (Bipolar)
12 74 0 –2 SIGNAL-TO-NOISE + DISTORTION (dB) THD f 11 68 –10 SAMPLE = 2.22MHz SFDR –8 10 62 –20 2ND –14 9 56 –30 3RD –20 f 8 50 –40 SAMPLE = 2.22MHz –26 7 44 –50 –32 6 38 –60 –38 5 32 –70 SNR (dB) –44 4 26 –80 –50 3 20 THD, SFDR, 2ND 3RD (dB) –90 –56 EFFECTIVE NUMBER OF BITS 2 14 –100 –62 1 8 –110 –68 fSAMPLE = 2.22MHz 0 2 –120 –74 104 105 106 107 104 105 106 107 104 105 106 107 INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) 1401 G01 1401 G02 1401 G03
5 Harmonic THD, 2nd, 3rd and ENOBs and SINAD SFDR vs Input Frequency vs Input Frequency (Unipolar) (Unipolar) SNR vs Input Frequency (Unipolar)
12 74 0 –2 SIGNAL-TO-NOISE + DISTORTION (dB) THD f 11 68 –10 SAMPLE = 2.22MHz SFDR –8 10 62 –20 2ND –14 9 56 –30 3RD –20 f 8 50 –40 SAMPLE = 2.22MHz –26 7 44 –50 –32 6 38 –60 –38 5 32 –70 SNR (dB) –44 4 26 –80 –50 3 20 THD, SFDR, 2ND 3RD (dB) –90 –56 EFFECTIVE NUMBER OF BITS 2 14 –100 –62 1 8 –110 –68 fSAMPLE = 2.22MHz 0 2 –120 –74 104 105 106 107 104 105 106 107 104 105 106 107 INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) 1401 G04 1401 G05 1401 G06 5
ELECTRICAL CHARACTERISTICS Note 12:
The absolute voltage at A + – IN and AIN must be within this range.
Note 16:
The time period for acquiring the input signal is started by the
Note 13:
If less than 7.3ns is allowed, the output data will appear one 14th rising clock and it is ended by the rising edge of convert. clock cycle later. It is best for CONV to rise half a clock before SCK, when
Note 17:
The internal reference settles in 2ms after it wakes up from Sleep running the clock at rated speed. mode with one or more cycles at SCK and a 10µF capacitive load. The
Note 14:
Not the same as aperture delay. Aperture delay is smaller (2.6ns) Sleep mode resets the REFREADY bit in the DOUT sequence. The because the 0.8ns delay through the sample-and-hold is subtracted from REFREADY bit goes high again 10ms after the VREF has stopped slewing in the CONV to Hold mode delay. wake up. This ensures valid REFREADY bit operation even with higher load
Note 15:
The rising edge of SCK is guaranteed to catch the data coming capacitances at VREF. out into a storage latch.
Note 18:
The full power bandwidth is the frequency where the output code swing drops to 2828LSBs with a 4VP-P input sine wave.
W U TYPICAL PERFOR A CE CHARACTERISTICS (Bipolar Mode Plots Run with Dual
±
5V Supplies. Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = – 5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25
°
C. 5 Harmonic THD, 2nd, 3rd and ENOBs and SINAD SFDR vs Input Frequency vs Input Frequency (Bipolar) (Bipolar) SNR vs Input Frequency (Bipolar)
12 74 0 –2 SIGNAL-TO-NOISE + DISTORTION (dB) THD f 11 68 –10 SAMPLE = 2.22MHz SFDR –8 10 62 –20 2ND –14 9 56 –30 3RD –20 f 8 50 –40 SAMPLE = 2.22MHz –26 7 44 –50 –32 6 38 –60 –38 5 32 –70 SNR (dB) –44 4 26 –80 –50 3 20 THD, SFDR, 2ND 3RD (dB) –90 –56 EFFECTIVE NUMBER OF BITS 2 14 –100 –62 1 8 –110 –68 fSAMPLE = 2.22MHz 0 2 –120 –74 104 105 106 107 104 105 106 107 104 105 106 107 INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) 1401 G01 1401 G02 1401 G03
5 Harmonic THD, 2nd, 3rd and ENOBs and SINAD SFDR vs Input Frequency vs Input Frequency (Unipolar) (Unipolar) SNR vs Input Frequency (Unipolar)
12 74 0 –2 SIGNAL-TO-NOISE + DISTORTION (dB) THD f 11 68 –10 SAMPLE = 2.22MHz SFDR –8 10 62 –20 2ND –14 9 56 –30 3RD –20 f 8 50 –40 SAMPLE = 2.22MHz –26 7 44 –50 –32 6 38 –60 –38 5 32 –70 SNR (dB) –44 4 26 –80 –50 3 20 THD, SFDR, 2ND 3RD (dB) –90 –56 EFFECTIVE NUMBER OF BITS 2 14 –100 –62 1 8 –110 –68 fSAMPLE = 2.22MHz 0 2 –120 –74 104 105 106 107 104 105 106 107 104 105 106 107 INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) 1401 G04 1401 G05 1401 G06 5
