Datasheet LTC1402 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Serial 12-Bit, 2.2Msps Sampling ADC with Shutdown |
| Pages / Page | 24 / 8 — PIN FUNCTIONS. GAIN (Pin 7):. DGND (Pin 13):. VSS (Pin 14):. BIP/UNI (Pin … |
| File Format / Size | PDF / 292 Kb |
| Document Language | English |
PIN FUNCTIONS. GAIN (Pin 7):. DGND (Pin 13):. VSS (Pin 14):. BIP/UNI (Pin 8):. OGND (Pin 9):. SCK (Pin 15):. OUT (Pin 10):
Model Line for this Datasheet
Text Version of Document
LTC1402
U U U PIN FUNCTIONS GAIN (Pin 7):
Tie to AGND2 to set the reference voltage to
DGND (Pin 13):
Digital Ground for Internal Logic. Tie to 4.096V or tie to VREF to set the reference voltage to 2.048V. solid analog ground plane. (Note 4)
VSS (Pin 14):
Negative Supply Voltage. Bypass to solid
BIP/UNI (Pin 8):
Tie to logic low to set the input range to analog ground plane with 10µF ceramic (or 10µF tantalum unipolar mode or tie to logic high to set the input range to in parallel with 0.1µF ceramic) or tie directly to the solid bipolar mode. (Note 4) analog ground plane for single supply use. Must be set + –
OGND (Pin 9):
Output Ground for the Output Driver. This more negative than either AIN or AIN . Set to 0V or – 5V. pin can be tied to the digital ground of the system. All other
SCK (Pin 15):
External Clock. Advances the conversion ground pins should be tied to the analog ground plane. process and sequences the output data at DOUT on the
D
rising edge. Responds to 5V or 3V CMOS and to TTL levels.
OUT (Pin 10):
Three-State Data Output. (Note 3) Each output data word represents the analog input at the start (Note 4). One or more pulses wake from Nap or Sleep. of the previous conversion.
CONV (Pin 16):
Holds the input analog signal and starts
OV
the conversion on the rising edge. Responds to 5V or 3V
DD (Pin 11):
Output Data Driver Power. Tie to VDD when driving 5V logic. Tie to 3V when driving 3V logic. CMOS and to TTL levels. (Note 4). Two pulses with SCK in fixed high or fixed low state start Nap Mode. Four pulses
DVDD (Pin 12):
Digital Power for Internal Logic. Bypass to with SCK in fixed high or fixed low state start Sleep mode. DGND with 10µF ceramic (or 10µF tantalum in parallel with 0.1µF ceramic).
W BLOCK DIAGRA
CSAMPLE A + 3 IN 1 AVDD CSAMPLE 12 DVDD 4 – 14 AIN VSS ZEROING SWITCHES 2.048V REF + + REF AMP 12-BIT CAPACITIVE DAC COMP – – 64k 7 64k GAIN 8 5 BIP/UNI VREF SUCCESSIVE APPROXIMATION OUTPUT 10 6 D AGND2 REGISTER DRIVER OUT 2 11 AGND1 OVDD 13 INTERNAL 9 CONTROL LOGIC DGND CLOCK OGND 16 15 1402 BD CONV SCK 8
U U U PIN FUNCTIONS GAIN (Pin 7):
Tie to AGND2 to set the reference voltage to
DGND (Pin 13):
Digital Ground for Internal Logic. Tie to 4.096V or tie to VREF to set the reference voltage to 2.048V. solid analog ground plane. (Note 4)
VSS (Pin 14):
Negative Supply Voltage. Bypass to solid
BIP/UNI (Pin 8):
Tie to logic low to set the input range to analog ground plane with 10µF ceramic (or 10µF tantalum unipolar mode or tie to logic high to set the input range to in parallel with 0.1µF ceramic) or tie directly to the solid bipolar mode. (Note 4) analog ground plane for single supply use. Must be set + –
OGND (Pin 9):
Output Ground for the Output Driver. This more negative than either AIN or AIN . Set to 0V or – 5V. pin can be tied to the digital ground of the system. All other
SCK (Pin 15):
External Clock. Advances the conversion ground pins should be tied to the analog ground plane. process and sequences the output data at DOUT on the
D
rising edge. Responds to 5V or 3V CMOS and to TTL levels.
OUT (Pin 10):
Three-State Data Output. (Note 3) Each output data word represents the analog input at the start (Note 4). One or more pulses wake from Nap or Sleep. of the previous conversion.
CONV (Pin 16):
Holds the input analog signal and starts
OV
the conversion on the rising edge. Responds to 5V or 3V
DD (Pin 11):
Output Data Driver Power. Tie to VDD when driving 5V logic. Tie to 3V when driving 3V logic. CMOS and to TTL levels. (Note 4). Two pulses with SCK in fixed high or fixed low state start Nap Mode. Four pulses
DVDD (Pin 12):
Digital Power for Internal Logic. Bypass to with SCK in fixed high or fixed low state start Sleep mode. DGND with 10µF ceramic (or 10µF tantalum in parallel with 0.1µF ceramic).
W BLOCK DIAGRA
CSAMPLE A + 3 IN 1 AVDD CSAMPLE 12 DVDD 4 – 14 AIN VSS ZEROING SWITCHES 2.048V REF + + REF AMP 12-BIT CAPACITIVE DAC COMP – – 64k 7 64k GAIN 8 5 BIP/UNI VREF SUCCESSIVE APPROXIMATION OUTPUT 10 6 D AGND2 REGISTER DRIVER OUT 2 11 AGND1 OVDD 13 INTERNAL 9 CONTROL LOGIC DGND CLOCK OGND 16 15 1402 BD CONV SCK 8
