Datasheet LTC1403, LTC1403A (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Serial 14-Bit, 2.8Msps Sampling ADCs with Shutdown |
| Pages / Page | 22 / 1 — Features. Description. 2.8Msps Conversion Rate. Low Power Dissipation: … |
| File Format / Size | PDF / 370 Kb |
| Document Language | English |
Features. Description. 2.8Msps Conversion Rate. Low Power Dissipation: 14mW. 3V Single Supply Operation
Model Line for this Datasheet
Text Version of Document
LTC1403/LTC1403A Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown
Features Description
n
2.8Msps Conversion Rate
The LTC®1403/LTC1403A are 12-bit/14-bit, 2.8Msps se- n
Low Power Dissipation: 14mW
rial ADCs with differential inputs. The devices draw only n
3V Single Supply Operation
4.7mA from a single 3V supply and come in a tiny 10-lead n
–40°C to 125°C Guaranteed Operation
MS package. A Sleep shutdown feature lowers power n 2.5V Internal Bandgap Reference can be Overdriven consumption to 10µW. The combination of speed, low n 3-Wire Serial Interface power and tiny package makes the LTC1403/LTC1403A n Sleep (10µW) Shutdown Mode suitable for high speed, portable applications. n Nap (3mW) Shutdown Mode The 80dB common mode rejection allows users to eliminate n 80dB Common Mode Rejection ground loops and common mode noise by measuring n 0V to 2.5V Unipolar Input Range signals differentially from the source. n Tiny 10-Lead MS Package The devices convert 0V to 2.5V unipolar inputs differentially.
applications
The absolute voltage swing for +AIN and –AIN extends from ground to the supply voltage. n Automotive The serial interface sends out the conversion results during n Communications the 16 clock cycles following CONV↑ for compatibility with n Data Acquisition Systems standard serial interfaces. If two additional clock cycles n Uninterrupted Power Supplies for acquisition time are allowed after the data stream in n Multiphase Motor Control between conversions, the full sampling rate of 2.8Msps n Multiplexed Data Acquisition can be achieved with a 50.4MHz clock. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and LinearView and SoftSpan are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Block Diagram
10µF 3V
2nd, 3rd and SFDR vs Input Frequency
–44 7 LTC1403A VDD –50 –56 A + IN 1 + THREE- THD 2nd, SFDR TCH STATE –62 S & H 14-BIT ADC SERIAL 8 SDO –68 A – OUTPUT IN 2 – 14-BIT LA PORT –74 3rd 14 –80 VREF –86 3 10 CONV THD, 2nd, SFDR, 3rd (dB) –92 10F 2.5V TIMING REFERENCE LOGIC GND –98 4 9 SCK –104 1403A TA01 5 6 11 0.1 1 10 100 EXPOSED PAD FREQUENCY (MHz) 1403A TA02 1403fc For more information www.linear.com/LTC1403 1 Document Outline Features Applications Block Diagram Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Package Description Revision History Related Parts
Features Description
n
2.8Msps Conversion Rate
The LTC®1403/LTC1403A are 12-bit/14-bit, 2.8Msps se- n
Low Power Dissipation: 14mW
rial ADCs with differential inputs. The devices draw only n
3V Single Supply Operation
4.7mA from a single 3V supply and come in a tiny 10-lead n
–40°C to 125°C Guaranteed Operation
MS package. A Sleep shutdown feature lowers power n 2.5V Internal Bandgap Reference can be Overdriven consumption to 10µW. The combination of speed, low n 3-Wire Serial Interface power and tiny package makes the LTC1403/LTC1403A n Sleep (10µW) Shutdown Mode suitable for high speed, portable applications. n Nap (3mW) Shutdown Mode The 80dB common mode rejection allows users to eliminate n 80dB Common Mode Rejection ground loops and common mode noise by measuring n 0V to 2.5V Unipolar Input Range signals differentially from the source. n Tiny 10-Lead MS Package The devices convert 0V to 2.5V unipolar inputs differentially.
applications
The absolute voltage swing for +AIN and –AIN extends from ground to the supply voltage. n Automotive The serial interface sends out the conversion results during n Communications the 16 clock cycles following CONV↑ for compatibility with n Data Acquisition Systems standard serial interfaces. If two additional clock cycles n Uninterrupted Power Supplies for acquisition time are allowed after the data stream in n Multiphase Motor Control between conversions, the full sampling rate of 2.8Msps n Multiplexed Data Acquisition can be achieved with a 50.4MHz clock. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and LinearView and SoftSpan are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Block Diagram
10µF 3V
2nd, 3rd and SFDR vs Input Frequency
–44 7 LTC1403A VDD –50 –56 A + IN 1 + THREE- THD 2nd, SFDR TCH STATE –62 S & H 14-BIT ADC SERIAL 8 SDO –68 A – OUTPUT IN 2 – 14-BIT LA PORT –74 3rd 14 –80 VREF –86 3 10 CONV THD, 2nd, SFDR, 3rd (dB) –92 10F 2.5V TIMING REFERENCE LOGIC GND –98 4 9 SCK –104 1403A TA01 5 6 11 0.1 1 10 100 EXPOSED PAD FREQUENCY (MHz) 1403A TA02 1403fc For more information www.linear.com/LTC1403 1 Document Outline Features Applications Block Diagram Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Package Description Revision History Related Parts
