Datasheet LTC1403-1, LTC1403A-1 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Serial 14-Bit, 2.8Msps Sampling ADCs with Shutdown |
| Pages / Page | 24 / 1 — FEATURES. DESCRIPTION. 2.8Msps Conversion Rate. Low Power Dissipation: … |
| File Format / Size | PDF / 576 Kb |
| Document Language | English |
FEATURES. DESCRIPTION. 2.8Msps Conversion Rate. Low Power Dissipation: 14mW. 3V Single Supply Operation. APPLICATIONS
Model Line for this Datasheet
Text Version of Document
LTC1403-1/LTC1403A-1 Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown
FEATURES DESCRIPTION
n
2.8Msps Conversion Rate
The LTC®1403-1/LTC1403A-1 are 12-bit/14-bit, 2.8Msps n
Low Power Dissipation: 14mW
serial ADCs with differential inputs. The devices draw only n
3V Single Supply Operation
4.7mA from a single 3V supply and come in a tiny 10-lead n 2.5V Internal Bandgap Reference Can Be Overdriven MSE package. A Sleep shutdown feature lowers power n 3-Wire Serial Interface consumption to 10µW. The combination of speed, low n Sleep (10µW) Shutdown Mode power and tiny package makes the LTC1403-1/LTC1403A-1 n Nap (3mW) Shutdown Mode suitable for high speed, portable applications. n 80dB Common Mode Rejection The 80dB common mode rejection allows users to eliminate n ±1.25V Bipolar Input Range ground loops and common mode noise by measuring n Tiny 10-Lead MSE Package signals differentially from the source. The devices convert –1.25V to 1.25V bipolar inputs
APPLICATIONS
differentially. The absolute voltage swing for A + IN and A – IN extends from ground to the supply voltage. n Communications The serial interface sends out the conversion results during n Data Acquisition Systems the 16 clock cycles following CONV↑ for compatibility with n Uninterrupted Power Supplies standard serial interfaces. If two additional clock cycles n Multiphase Motor Control for acquisition time are allowed after the data stream in n Multiplexed Data Acquisition between conversions, the full sampling rate of 2.8Msps can be achieved with a 50.4MHz clock. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
BLOCK DIAGRAM THD, 2nd and 3rd vs Input
10µF 3V
Frequency for Differential Input Signals
–44 7 LTC1403A-1 VDD –50 –56 A + IN 1 + THREE- TCH STATE –62 S & H 14-BIT ADC SERIAL 8 SDO –68 A – OUTPUT IN 2 – 14-BIT LA PORT –74 THD 3rd 14 –80 VREF THD, 2nd, 3rd (dB) 3 10 CONV –86 2nd 10µF 2.5V TIMING –92 REFERENCE LOGIC GND –98 4 9 SCK –104 14031 TA01a 5 6 11 0.1 1 10 100 EXPOSED PAD FREQUENCY (MHz) 14031 TA01b 14031fd For more information www.linear.com/LTC1403-1 1 Document Outline Features Applications Description Block Diagram Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Revision History Related Parts
FEATURES DESCRIPTION
n
2.8Msps Conversion Rate
The LTC®1403-1/LTC1403A-1 are 12-bit/14-bit, 2.8Msps n
Low Power Dissipation: 14mW
serial ADCs with differential inputs. The devices draw only n
3V Single Supply Operation
4.7mA from a single 3V supply and come in a tiny 10-lead n 2.5V Internal Bandgap Reference Can Be Overdriven MSE package. A Sleep shutdown feature lowers power n 3-Wire Serial Interface consumption to 10µW. The combination of speed, low n Sleep (10µW) Shutdown Mode power and tiny package makes the LTC1403-1/LTC1403A-1 n Nap (3mW) Shutdown Mode suitable for high speed, portable applications. n 80dB Common Mode Rejection The 80dB common mode rejection allows users to eliminate n ±1.25V Bipolar Input Range ground loops and common mode noise by measuring n Tiny 10-Lead MSE Package signals differentially from the source. The devices convert –1.25V to 1.25V bipolar inputs
APPLICATIONS
differentially. The absolute voltage swing for A + IN and A – IN extends from ground to the supply voltage. n Communications The serial interface sends out the conversion results during n Data Acquisition Systems the 16 clock cycles following CONV↑ for compatibility with n Uninterrupted Power Supplies standard serial interfaces. If two additional clock cycles n Multiphase Motor Control for acquisition time are allowed after the data stream in n Multiplexed Data Acquisition between conversions, the full sampling rate of 2.8Msps can be achieved with a 50.4MHz clock. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
BLOCK DIAGRAM THD, 2nd and 3rd vs Input
10µF 3V
Frequency for Differential Input Signals
–44 7 LTC1403A-1 VDD –50 –56 A + IN 1 + THREE- TCH STATE –62 S & H 14-BIT ADC SERIAL 8 SDO –68 A – OUTPUT IN 2 – 14-BIT LA PORT –74 THD 3rd 14 –80 VREF THD, 2nd, 3rd (dB) 3 10 CONV –86 2nd 10µF 2.5V TIMING –92 REFERENCE LOGIC GND –98 4 9 SCK –104 14031 TA01a 5 6 11 0.1 1 10 100 EXPOSED PAD FREQUENCY (MHz) 14031 TA01b 14031fd For more information www.linear.com/LTC1403-1 1 Document Outline Features Applications Description Block Diagram Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Revision History Related Parts
