Datasheet LTC1403-1, LTC1403A-1 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Serial 14-Bit, 2.8Msps Sampling ADCs with Shutdown |
| Pages / Page | 24 / 5 — ELECTRICAL CHARACTERISTICS. Note 1:. Note 11:. Note 12:. Note 2:. Note … |
| File Format / Size | PDF / 576 Kb |
| Document Language | English |
ELECTRICAL CHARACTERISTICS. Note 1:. Note 11:. Note 12:. Note 2:. Note 3:. Note 13:. Note 14:. Note 4:. Note 15:. Note 5:. Note 16:. Note 17:
Model Line for this Datasheet
Text Version of Document
LTC1403-1/LTC1403A-1
ELECTRICAL CHARACTERISTICS Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 11:
Not the same as aperture delay. Aperture delay is smaller (1ns) may cause permanent damage to the device. Exposure to any Absolute because the 2.2ns delay through the sample-and-hold is subtracted from Maximum Rating condition for extended periods may affect device the CONV to Hold mode delay. reliability and lifetime.
Note 12:
The rising edge of SCK is guaranteed to catch the data coming
Note 2:
All voltage values are with respect to GND. out into a storage latch.
Note 3:
When these pins are taken below GND or above VDD, they will be
Note 13:
The time period for acquiring the input signal is started by the clamped by internal diodes. This product can handle input currents greater 16th rising clock and it is ended by the rising edge of convert. than 100mA below GND or greater than VDD without latchup.
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep
Note 4:
Offset and full-scale specifications are measured for a single- mode with one or more cycles at SCK and a 10µF capacitive load. ended A + – IN input with AIN grounded and using the internal 2.5V reference.
Note 15:
The full power bandwidth is the frequency where the output code
Note 5:
Integral linearity is tested with an external 2.55V reference and is swing drops to 3dB with a 2.5VP-P input sine wave. defined as the deviation of a code from the straight line passing through
Note 16:
Maximum clock period guarantees analog performance during the actual endpoints of a transfer curve. The deviation is measured from conversion. Output data can be read without an arbitrarily long clock. the center of quantization band.
Note 17:
VDD = 3V, fSAMPLE = 2.8Msps.
Note 6:
Guaranteed by design, not subject to test.
Note 18:
The LTC1403A-1 is measured and specified with 14-bit
Note 7:
Recommended operating conditions. Resolution (1LSB = 152µV) and the LTC1403-1 is measured and specified
Note 8:
The analog input range is defined for the voltage difference with 12-bit Resolution (1LSB = 610µV). between A + – – IN and AIN . Performance is specified with AIN = 1.5V DC while
Note 19:
Full-scale sinewaves are fed into the noninverting input while the driving A + IN . inverting input is kept at 1.5V DC.
Note 9:
The absolute voltage at A + – IN and AIN must be within this range.
Note 20:
The sampling capacitor at each input accounts for 4.1pF of the
Note 10:
If less than 3ns is allowed, the output data will appear one input capacitance. clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. 14031fd For more information www.linear.com/LTC1403-1 5 Document Outline Features Applications Description Block Diagram Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Revision History Related Parts
ELECTRICAL CHARACTERISTICS Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 11:
Not the same as aperture delay. Aperture delay is smaller (1ns) may cause permanent damage to the device. Exposure to any Absolute because the 2.2ns delay through the sample-and-hold is subtracted from Maximum Rating condition for extended periods may affect device the CONV to Hold mode delay. reliability and lifetime.
Note 12:
The rising edge of SCK is guaranteed to catch the data coming
Note 2:
All voltage values are with respect to GND. out into a storage latch.
Note 3:
When these pins are taken below GND or above VDD, they will be
Note 13:
The time period for acquiring the input signal is started by the clamped by internal diodes. This product can handle input currents greater 16th rising clock and it is ended by the rising edge of convert. than 100mA below GND or greater than VDD without latchup.
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep
Note 4:
Offset and full-scale specifications are measured for a single- mode with one or more cycles at SCK and a 10µF capacitive load. ended A + – IN input with AIN grounded and using the internal 2.5V reference.
Note 15:
The full power bandwidth is the frequency where the output code
Note 5:
Integral linearity is tested with an external 2.55V reference and is swing drops to 3dB with a 2.5VP-P input sine wave. defined as the deviation of a code from the straight line passing through
Note 16:
Maximum clock period guarantees analog performance during the actual endpoints of a transfer curve. The deviation is measured from conversion. Output data can be read without an arbitrarily long clock. the center of quantization band.
Note 17:
VDD = 3V, fSAMPLE = 2.8Msps.
Note 6:
Guaranteed by design, not subject to test.
Note 18:
The LTC1403A-1 is measured and specified with 14-bit
Note 7:
Recommended operating conditions. Resolution (1LSB = 152µV) and the LTC1403-1 is measured and specified
Note 8:
The analog input range is defined for the voltage difference with 12-bit Resolution (1LSB = 610µV). between A + – – IN and AIN . Performance is specified with AIN = 1.5V DC while
Note 19:
Full-scale sinewaves are fed into the noninverting input while the driving A + IN . inverting input is kept at 1.5V DC.
Note 9:
The absolute voltage at A + – IN and AIN must be within this range.
Note 20:
The sampling capacitor at each input accounts for 4.1pF of the
Note 10:
If less than 3ns is allowed, the output data will appear one input capacitance. clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. 14031fd For more information www.linear.com/LTC1403-1 5 Document Outline Features Applications Description Block Diagram Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Revision History Related Parts
