Datasheet LTC1406 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Low Power, 8-Bit, 20Msps, Sampling A/D Converter |
| Pages / Page | 16 / 4 — W U. TI I G CHARACTERISTICS The |
| File Format / Size | PDF / 381 Kb |
| Document Language | English |
W U. TI I G CHARACTERISTICS The
Model Line for this Datasheet
Text Version of Document
LTC1406
W U TI I G CHARACTERISTICS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL(MAX) Maximum Sampling Frequency ● 20 MHz t1 Clock Period (Notes 11, 12) ● 50 ns t2 Pulse Width High (Notes 11, 12) ● 25 ns t3 Pulse Width Low (Notes 11, 12) ● 25 ns t4 Output Delay CL = 15pF 15 25 ns t5 Pipeline Delay 5 Cycles t6 Aperture Delay 3 ns Aperture Jitter 5 psRMS
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 7:
Integral nonlinearity is defined as the deviation of a code from a of a device may be impaired. straight line passing through the actual endpoints of the transfer curve.
Note 2:
All voltage values are with respect to ground with DGND, OGND The deviation is measured from the center of the quantization band. and AGND wired together (unless otherwise noted).
Note 8:
Bipolar offset is the offset voltage measured from – 0.5LSB
Note 3:
When these pin voltages are taken below ground or above V when the output code flickers between 0111 1111 and 1000 0000. DD, they will be clamped by internal diodes. This product can handle input
Note 9:
Guaranteed by design, not subject to test. currents greater than 100mA below ground or above VDD without latchup.
Note 10:
Recommended operating conditions.
Note 4:
When these pin voltages are taken below ground they will be
Note 11:
The falling CLK edge starts a conversion. clamped by internal diodes. This product can handle input currents up to
Note 12:
At the maximum conversion rate, deviation from a 50% duty 100mA below ground without latchup. These pins are not clamped to VDD. cycle results in interstage settling times < 25ns and performance may
Note 5:
VDD = 5V, fSMPL = 20MHz and tr = tf = 2ns unless otherwise be affected. specified.
Note 13:
VIN = – Full Scale.
Note 6:
Linearity, offset and full-scale specifications apply for a single- ended A + – IN input with AIN tied to VREF = 2.5V.
W U TYPICAL PERFORMANCE CHARACTERISTICS Signal-to-Noise Ratio vs S/(N + D) vs Input Frequency Input Frequency Distortion vs Input Frequency
52 52 0 48 48 –10 44 44 40 40 –20 36 36 32 –30 32 28 28 –40 24 24 S/(N + D) (dB) 20 20 –50 16 16 –60 THD 12 12 SIGNAL-TO-NOISE RATIO (dB) 8 8 –70 3RD HARMONIC 4 4 2ND HARMONIC AMPLITUDE (dB BELOW THE FUNDAMENTAL) 0 0 –80 100k 1M 10M 100M 100k 1M 10M 100M 100k 1M 10M 100M INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) 1406 G01 1406 G02 1406 G03 4
W U TI I G CHARACTERISTICS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL(MAX) Maximum Sampling Frequency ● 20 MHz t1 Clock Period (Notes 11, 12) ● 50 ns t2 Pulse Width High (Notes 11, 12) ● 25 ns t3 Pulse Width Low (Notes 11, 12) ● 25 ns t4 Output Delay CL = 15pF 15 25 ns t5 Pipeline Delay 5 Cycles t6 Aperture Delay 3 ns Aperture Jitter 5 psRMS
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 7:
Integral nonlinearity is defined as the deviation of a code from a of a device may be impaired. straight line passing through the actual endpoints of the transfer curve.
Note 2:
All voltage values are with respect to ground with DGND, OGND The deviation is measured from the center of the quantization band. and AGND wired together (unless otherwise noted).
Note 8:
Bipolar offset is the offset voltage measured from – 0.5LSB
Note 3:
When these pin voltages are taken below ground or above V when the output code flickers between 0111 1111 and 1000 0000. DD, they will be clamped by internal diodes. This product can handle input
Note 9:
Guaranteed by design, not subject to test. currents greater than 100mA below ground or above VDD without latchup.
Note 10:
Recommended operating conditions.
Note 4:
When these pin voltages are taken below ground they will be
Note 11:
The falling CLK edge starts a conversion. clamped by internal diodes. This product can handle input currents up to
Note 12:
At the maximum conversion rate, deviation from a 50% duty 100mA below ground without latchup. These pins are not clamped to VDD. cycle results in interstage settling times < 25ns and performance may
Note 5:
VDD = 5V, fSMPL = 20MHz and tr = tf = 2ns unless otherwise be affected. specified.
Note 13:
VIN = – Full Scale.
Note 6:
Linearity, offset and full-scale specifications apply for a single- ended A + – IN input with AIN tied to VREF = 2.5V.
W U TYPICAL PERFORMANCE CHARACTERISTICS Signal-to-Noise Ratio vs S/(N + D) vs Input Frequency Input Frequency Distortion vs Input Frequency
52 52 0 48 48 –10 44 44 40 40 –20 36 36 32 –30 32 28 28 –40 24 24 S/(N + D) (dB) 20 20 –50 16 16 –60 THD 12 12 SIGNAL-TO-NOISE RATIO (dB) 8 8 –70 3RD HARMONIC 4 4 2ND HARMONIC AMPLITUDE (dB BELOW THE FUNDAMENTAL) 0 0 –80 100k 1M 10M 100M 100k 1M 10M 100M 100k 1M 10M 100M INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) 1406 G01 1406 G02 1406 G03 4
