LTC1406 UUUPIN FUNCTIONSAVD7 to D0 (Pins 15 to 22): Digital Data Outputs. The out- DD (Pin 9): Analog 5V Positive Supply. Bypass to ana- log ground plane with 10µF tantalum in parallel with 0.1µF puts swing between OVDD and OGND. or 10µF ceramic. OF/UF (Pin 23): Overflow/Underflow Bit. OF/UF high with AGND (Pin 10): Analog Ground. Tie to analog ground plane. D7 to D0 all high indicates an overrange, OF/UF high with D7 to D0 all low indicates an underrange condition. OF/UF DGND (Pin 11): Digital Ground for Internal Logic. Tie to low indicates a conversion within the normal input range. analog ground plane. The outputs swing between OVDD and OGND. DVDD (Pin 12): Digital 5V Positive Supply. Bypass to DGND CLK (Pin 24): Clock Input. Internal sample-and-hold tracks with 10µF tantalum in parallel with 0.1µF or 10µF ceramic. the input signal when CLK is high and samples the input NC (Pins 13, 14): No Internal Connection. signal on the falling edge. AVDD = DVDD = VDDNOMINAL (V)ABSOLUTE MAXIMUM (V)PINNAMEDESCRIPTIONMINTYPMAXMINMAX 1 OGND Ground for Output Drivers 0 – 0.3 VDD + 0.3 2 OVDD Supply for Output Drivers 2.7 3 or 5 5.25 – 0.3 6 3 SHDN Shutdown Input, Active Low 0 VDD – 0.3 10 4 VBIAS Internal Bias Voltage 1.9 2.2 2.5 – 0.3 VDD + 0.3 5 VREF External Reference Input 2 2.5 3 – 0.3 VDD + 0.3 6 AGND Analog Ground, Clean Ground 0 – 0.3 VDD + 0.3 7 A + IN Positive Analog Input, ±1V Span 0 VDD – 0.3 VDD + 0.3 8 A – IN Negative Analog Input 0 VDD – 0.3 VDD + 0.3 9 AVDD Analog Supply 4.75 5 5.25 – 0.3 6 10 AGND Analog Ground, Substrate Ground 0 – 0.3 VDD + 0.3 11 DGND Digital Ground 0 – 0.3 VDD + 0.3 12 DVDD Digital Supply 4.75 5 5.25 – 0.3 6 13 to 14 NC No Connect, No Internal Connection 15 to 22 D7 to D0 Data Outputs OGND OVDD – 0.3 VDD + 0.3 23 OF/UF Overflow/Underflow Output OGND OVDD – 0.3 VDD + 0.3 24 CLK Clock Input 0 VDD – 0.3 10 W UWTI I G DIAGRA t6 N N + 1 ANALOG N + 2 SIGNAL N – 1 N + 3 N + 6 N + 4 N + 5 t3 t1 CLOCK t2 t4 DATA OUT N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N 1406 TD t5 6