Datasheet LTC1409 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 12-Bit, 800ksps Sampling A/D Converter with Shutdown |
| Pages / Page | 20 / 7 — PI FU CTIO S. CONVST (Pin 23):. VSS (Pin 26):. CS (Pin 24):. OVDD (Pin … |
| File Format / Size | PDF / 356 Kb |
| Document Language | English |
PI FU CTIO S. CONVST (Pin 23):. VSS (Pin 26):. CS (Pin 24):. OVDD (Pin 27):. BUSY (Pin 25):. AVDD (Pin 28):. FU CTIO AL BLOCK DIAGRA
Model Line for this Datasheet
Text Version of Document
LTC1409
U U U PI FU CTIO S CONVST (Pin 23):
Conversion Start Signal. This active
VSS (Pin 26):
– 5V Negative Supply. Bypass to AGND low signal starts a conversion on its falling edge. using 10µF tantalum in parallel 0.1µF or 10µF ceramic.
CS (Pin 24):
Chip Select. The input must be low for the
OVDD (Pin 27):
Positive Supply for Output Drivers. For ADC to recognize CONVST and RD inputs. 5V logic, short to Pin 28. For 3V logic, short to supply
BUSY (Pin 25):
The BUSY output shows the converter of the logic being driven. status. It is low when a conversion is in progress. Data
AVDD (Pin 28):
5V Positive Supply. Bypass to AGND valid on the rising edge of BUSY. 10µF tantalum in parallel with 0.1µF or 10µF ceramic.
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE +AIN AVDD CSAMPLE – AIN 4k ZEROING SWITCHES VREF 2.5V REF + REF AMP 12-BIT CAPACITIVE DAC COMP – OV REFCOMP DD (4.06V) 12 SUCCESSIVE APPROXIMATION • D11 OUTPUT LATCHES • REGISTER • D0 AGND OGND INTERNAL CONTROL LOGIC DGND CLOCK LTC1409 • BD NAP/SLP SHDN RD CONVST CS BUSY
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Bus Relinquish Time
5V 5V 1k 1k DBN DBN DBN DBN 1k CL CL 1k 100pF 100pF LTC1409 • TC01 LTC1409 • TC02
(a) Hi-Z to VOH (b) Hi-Z to VOL (a) VOH to Hi-Z (b) VOL to Hi-Z and VOL to VOH and VOH to VOL
7
U U U PI FU CTIO S CONVST (Pin 23):
Conversion Start Signal. This active
VSS (Pin 26):
– 5V Negative Supply. Bypass to AGND low signal starts a conversion on its falling edge. using 10µF tantalum in parallel 0.1µF or 10µF ceramic.
CS (Pin 24):
Chip Select. The input must be low for the
OVDD (Pin 27):
Positive Supply for Output Drivers. For ADC to recognize CONVST and RD inputs. 5V logic, short to Pin 28. For 3V logic, short to supply
BUSY (Pin 25):
The BUSY output shows the converter of the logic being driven. status. It is low when a conversion is in progress. Data
AVDD (Pin 28):
5V Positive Supply. Bypass to AGND valid on the rising edge of BUSY. 10µF tantalum in parallel with 0.1µF or 10µF ceramic.
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE +AIN AVDD CSAMPLE – AIN 4k ZEROING SWITCHES VREF 2.5V REF + REF AMP 12-BIT CAPACITIVE DAC COMP – OV REFCOMP DD (4.06V) 12 SUCCESSIVE APPROXIMATION • D11 OUTPUT LATCHES • REGISTER • D0 AGND OGND INTERNAL CONTROL LOGIC DGND CLOCK LTC1409 • BD NAP/SLP SHDN RD CONVST CS BUSY
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Bus Relinquish Time
5V 5V 1k 1k DBN DBN DBN DBN 1k CL CL 1k 100pF 100pF LTC1409 • TC01 LTC1409 • TC02
(a) Hi-Z to VOH (b) Hi-Z to VOL (a) VOH to Hi-Z (b) VOL to Hi-Z and VOL to VOH and VOH to VOL
7
