Datasheet LTC1409 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 12-Bit, 800ksps Sampling A/D Converter with Shutdown |
| Pages / Page | 20 / 8 — APPLICATIONS INFORMATION. CONVERSION DETAILS. DYNAMIC PERFORMANCE. Figure … |
| File Format / Size | PDF / 356 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. CONVERSION DETAILS. DYNAMIC PERFORMANCE. Figure 2a. LTC1409 Nonaveraged, 4096 Point FFT,
Model Line for this Datasheet
Text Version of Document
LTC1409
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the The LTC1409 uses a successive approximation algorithm differential DACs output balances the +A and an internal sample-and-hold circuit to convert an IN and –AIN input charges. The SAR contents (a 12-bit data word) which analog signal to a 12-bit parallel output. The ADC is represents the difference of +AIN and –AIN are loaded into complete with a precision reference and an internal clock. the 12-bit output latches. The control logic provides easy interface to microproces- sors and DSPs. (Please refer to the Digital Interface
DYNAMIC PERFORMANCE
section for the data format.) The LTC1409 has excellent high speed sampling capabil- Conversion start is controlled by the CS and CONVST ity. FFT (Fast Four Transform) test techniques are used to inputs. At the start of the conversion the successive test the ADC’s frequency response, distortion and noise at approximation register (SAR) is reset. Once a conversion the rated throughput. By applying a low distortion sine cycle has begun it cannot be restarted. wave and analyzing the digital output using FFT algorithm, During the conversion, the internal differential 12-bit the ADC’s spectral content can be examined for frequen- capacitive DAC output is sequenced by the SAR from the cies outside the fundamental. Figure 2 shows typical most significant bit (MSB) to the least significant bit LTC1409 plots. (LSB). Referring to Figure 1, the +AIN and –AIN inputs are connected to the sample-and-hold capacitors (C 0 SAMPLE) fSAMPLE = 800kHz during the acquire phase and the comparator offset is fIN = 97.45kHz –20 SFDR = 89.1dB nulled by the zeroing switches. In this acquire phase, a SINAD = 73.1dB minimum delay of 150ns will provide enough time for the –40 sample-and-hold capacitors to acquire the analog signal. –60 During the convert phase the comparator zeroing switches open, putting the comparator into compare mode. The AMPLITUDE (dB) –80 input switches connect the CSAMPLE capacitors to ground, –100 transferring the differential analog input charge onto the summing junction. This input charge is successively com- –120 0 50 100 150 200 250 300 350 400 pared with the binary-weighted charges supplied by the FREQUENCY (kHz) LT1409 • F02a
Figure 2a. LTC1409 Nonaveraged, 4096 Point FFT,
+CSAMPLE
Input Frequency = 100kHz
+AIN HOLD ZEROING SWITCHES 0 –C fSAMPLE = 800kHz SAMPLE HOLD fIN = 375kHz –A –20 IN SFDR = 89dB HOLD SINAD = 72.5dB HOLD –40 +CDAC + –60 –C COMP DAC +V AMPLITUDE (dB) DAC –80 – –100 –VDAC 12 –120 • D11 SAR OUTPUT • 0 50 100 150 200 250 300 350 400 LATCHES • D0 FREQUENCY (kHz) LT1409 • F02b LTC1409 • F01
Figure 2b. LTC1409 Nonaveraged, 4096 Point FFT, Figure 1. Simplified Block Diagram Input Frequency = 375kHz
8
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the The LTC1409 uses a successive approximation algorithm differential DACs output balances the +A and an internal sample-and-hold circuit to convert an IN and –AIN input charges. The SAR contents (a 12-bit data word) which analog signal to a 12-bit parallel output. The ADC is represents the difference of +AIN and –AIN are loaded into complete with a precision reference and an internal clock. the 12-bit output latches. The control logic provides easy interface to microproces- sors and DSPs. (Please refer to the Digital Interface
DYNAMIC PERFORMANCE
section for the data format.) The LTC1409 has excellent high speed sampling capabil- Conversion start is controlled by the CS and CONVST ity. FFT (Fast Four Transform) test techniques are used to inputs. At the start of the conversion the successive test the ADC’s frequency response, distortion and noise at approximation register (SAR) is reset. Once a conversion the rated throughput. By applying a low distortion sine cycle has begun it cannot be restarted. wave and analyzing the digital output using FFT algorithm, During the conversion, the internal differential 12-bit the ADC’s spectral content can be examined for frequen- capacitive DAC output is sequenced by the SAR from the cies outside the fundamental. Figure 2 shows typical most significant bit (MSB) to the least significant bit LTC1409 plots. (LSB). Referring to Figure 1, the +AIN and –AIN inputs are connected to the sample-and-hold capacitors (C 0 SAMPLE) fSAMPLE = 800kHz during the acquire phase and the comparator offset is fIN = 97.45kHz –20 SFDR = 89.1dB nulled by the zeroing switches. In this acquire phase, a SINAD = 73.1dB minimum delay of 150ns will provide enough time for the –40 sample-and-hold capacitors to acquire the analog signal. –60 During the convert phase the comparator zeroing switches open, putting the comparator into compare mode. The AMPLITUDE (dB) –80 input switches connect the CSAMPLE capacitors to ground, –100 transferring the differential analog input charge onto the summing junction. This input charge is successively com- –120 0 50 100 150 200 250 300 350 400 pared with the binary-weighted charges supplied by the FREQUENCY (kHz) LT1409 • F02a
Figure 2a. LTC1409 Nonaveraged, 4096 Point FFT,
+CSAMPLE
Input Frequency = 100kHz
+AIN HOLD ZEROING SWITCHES 0 –C fSAMPLE = 800kHz SAMPLE HOLD fIN = 375kHz –A –20 IN SFDR = 89dB HOLD SINAD = 72.5dB HOLD –40 +CDAC + –60 –C COMP DAC +V AMPLITUDE (dB) DAC –80 – –100 –VDAC 12 –120 • D11 SAR OUTPUT • 0 50 100 150 200 250 300 350 400 LATCHES • D0 FREQUENCY (kHz) LT1409 • F02b LTC1409 • F01
Figure 2b. LTC1409 Nonaveraged, 4096 Point FFT, Figure 1. Simplified Block Diagram Input Frequency = 375kHz
8
