Datasheet LTC1410 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 12-Bit, 1.25Msps, Sampling A/D Converter with Shutdown |
| Pages / Page | 16 / 7 — TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output … |
| File Format / Size | PDF / 162 Kb |
| Document Language | English |
TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output Float Delay. APPLICATIONS INFORMATION
Model Line for this Datasheet
Text Version of Document
LTC1410
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DBN DBN DBN DBN 1k C 1k 100pF 100pF L CL (A) Hi-Z TO V (A) V OH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL OH TO Hi-Z (B) VOL TO Hi-Z 1410 TC01 1410 TC02
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
onto the summing junctions. This input charge is succes- The LTC1410 uses a successive approximation algorithm sively compared with the binarily-weighted charges sup- and an internal sample-and-hold circuit to convert an plied by the differential capacitive DAC. Bit decisions are analog signal to a 12-bit parallel output. The ADC is made by the high speed comparator. At the end of a complete with a precision reference and an internal clock. conversion, the differential DAC output balances the + AIN The control logic provides easy interface to microproces- and – AIN input charges. The SAR contents (a 12-bit data sors and DSPs. (Please refer to the Digital Interface word) which represent the difference of + AIN and – AIN are section for the data format.) loaded into the 12-bit output latches. Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion the successive +CSAMPLE approximation register (SAR) is reset. Once a conversion SAMPLE +AIN cycle has begun it cannot be restarted. HOLD ZEROING SWITCHES –CSAMPLE During the conversion, the internal differential 12-bit SAMPLE HOLD – AIN capacitive DAC output is sequenced by the SAR from the HOLD HOLD Most Significant Bit (MSB) to the Least Significant Bit +CDAC (LSB). Referring to Figure 1, the + AIN and – AIN inputs are + connected to the sample-and-hold capacitors (CSAMPLE) –CDAC COMP during the acquire phase and the comparator offset is +V – DAC nulled by the zeroing switches. In this acquire phase, a minimum duration of 100ns will provide enough time for –VDAC 12 D11 the sample-and-hold capacitors to acquire the analog OUTPUT • SAR • • LATCHES D0 signal. During the convert phase the comparator zeroing 1410 F01 switches open, putting the comparator into compare mode. The input switches connect the CSAMPLE capacitors
Figure 1. Simplified Block Diagram
to ground, transferring the differential analog input charge 7
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DBN DBN DBN DBN 1k C 1k 100pF 100pF L CL (A) Hi-Z TO V (A) V OH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL OH TO Hi-Z (B) VOL TO Hi-Z 1410 TC01 1410 TC02
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
onto the summing junctions. This input charge is succes- The LTC1410 uses a successive approximation algorithm sively compared with the binarily-weighted charges sup- and an internal sample-and-hold circuit to convert an plied by the differential capacitive DAC. Bit decisions are analog signal to a 12-bit parallel output. The ADC is made by the high speed comparator. At the end of a complete with a precision reference and an internal clock. conversion, the differential DAC output balances the + AIN The control logic provides easy interface to microproces- and – AIN input charges. The SAR contents (a 12-bit data sors and DSPs. (Please refer to the Digital Interface word) which represent the difference of + AIN and – AIN are section for the data format.) loaded into the 12-bit output latches. Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion the successive +CSAMPLE approximation register (SAR) is reset. Once a conversion SAMPLE +AIN cycle has begun it cannot be restarted. HOLD ZEROING SWITCHES –CSAMPLE During the conversion, the internal differential 12-bit SAMPLE HOLD – AIN capacitive DAC output is sequenced by the SAR from the HOLD HOLD Most Significant Bit (MSB) to the Least Significant Bit +CDAC (LSB). Referring to Figure 1, the + AIN and – AIN inputs are + connected to the sample-and-hold capacitors (CSAMPLE) –CDAC COMP during the acquire phase and the comparator offset is +V – DAC nulled by the zeroing switches. In this acquire phase, a minimum duration of 100ns will provide enough time for –VDAC 12 D11 the sample-and-hold capacitors to acquire the analog OUTPUT • SAR • • LATCHES D0 signal. During the convert phase the comparator zeroing 1410 F01 switches open, putting the comparator into compare mode. The input switches connect the CSAMPLE capacitors
Figure 1. Simplified Block Diagram
to ground, transferring the differential analog input charge 7
