Datasheet LTC1744 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 14-Bit, 50Msps ADC |
| Pages / Page | 24 / 9 — TYPICAL PERFOR A CE CHARACTERISTICS (Note 5). Input = 5MHz, –25dBFS,. … |
| File Format / Size | PDF / 556 Kb |
| Document Language | English |
TYPICAL PERFOR A CE CHARACTERISTICS (Note 5). Input = 5MHz, –25dBFS,. Input = 5MHz, –25dBFS, No Dither. Dither Applied
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LTC1744
W U TYPICAL PERFOR A CE CHARACTERISTICS (Note 5) Input = 5MHz, –25dBFS, Input = 5MHz, –25dBFS, No Dither Dither Applied
0.5 0.5 –10 TA = 25°C –10 TA = 25°C –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 AMPLITUDE (dB) –100 AMPLITUDE (dB) –100 –110 –110 –120 –120 –130 –130 –140 –140 –150 –150 0 2 4 6 8 10 12 14 16 18 20 22 24 0 2 4 6 8 10 12 14 16 18 20 22 24 FREQUENCY (MHz) 24.99 FREQUENCY (MHz) 24.99 1744 G36 1744 G37
U U U PI FU CTIO S SENSE (Pin 1):
Reference Sense Pin. Ground selects
MSBINV (Pin 22):
MSB Inversion Control. Low inverts ±1V. VDD selects ±1.6V. Greater than 1V and less than the MSB, 2’s complement output format. High does not 1.6V applied to the SENSE pin selects an input range of invert the MSB, offset binary output format. ±VSENSE, ±1.6V is the largest valid input range.
ENC (Pin 23):
Encode Input. The input sample starts on
VCM (Pin 2):
2.5V Output and Input Common Mode Bias. the positive edge. Bypass to ground with 4.7µF ceramic chip capacitor.
ENC (Pin 24):
Encode Complement Input. Conversion
GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37):
ADC starts on the negative edge. Bypass to ground with 0.1µF Power Ground. ceramic for single-ended encode signal.
A + IN (Pin 4):
Positive Differential Analog Input.
OE (Pin 25):
Output Enable. Low enables outputs. Logic
A –
high makes outputs Hi-Z.
IN (Pin 5):
Negative Differential Analog Input.
V CLKOUT (Pin 26):
Data Valid Output. Latch data on the
DD (Pins 7, 8, 17, 18, 20):
5V Supply. Bypass to AGND with 1µF ceramic chip capacitor. rising edge of CLKOUT.
REFLB (Pin 10):
ADC Low Reference. Bypass to Pin 11 with
OGND (Pins 27, 38, 47):
Output Driver Ground. 0.1µF ceramic chip capacitor. Do not connect to Pin␣ 14.
D0-D3 (Pins 28 to 31):
Digital Outputs. D0 is the LSB.
REFHA (Pin 11):
ADC High Reference. Bypass to Pin 10 with
OVDD (Pins 32, 43):
Positive Supply for the Output Driv- 0.1µF ceramic chip capacitor, to Pin 14 with a 4.7µF ceramic ers. Bypass to ground with 0.1µF ceramic chip capacitor. capacitor and to ground with 1µF ceramic capacitor.
D4-D6 (Pins 33 to 35):
Digital Outputs.
REFLA (Pin 14):
ADC Low Reference. Bypass to Pin 15 with
D7-D10 (Pins 39 to 42):
Digital Outputs. 0.1µF ceramic chip capacitor, to Pin 11 with a 4.7µF ceramic
D11-D13 (Pins 44 to 46):
Digital Outputs. D13 is the MSB. capacitor and to ground with 1µF ceramic capacitor.
OF (Pin 48):
Over/Under Flow Output. High when an over
REFHB (Pin 15):
ADC High Reference. Bypass to Pin 14 with or under flow has occurred. 0.1µF ceramic chip capacitor. Do not connect to Pin␣ 11. 1744f 9
W U TYPICAL PERFOR A CE CHARACTERISTICS (Note 5) Input = 5MHz, –25dBFS, Input = 5MHz, –25dBFS, No Dither Dither Applied
0.5 0.5 –10 TA = 25°C –10 TA = 25°C –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 AMPLITUDE (dB) –100 AMPLITUDE (dB) –100 –110 –110 –120 –120 –130 –130 –140 –140 –150 –150 0 2 4 6 8 10 12 14 16 18 20 22 24 0 2 4 6 8 10 12 14 16 18 20 22 24 FREQUENCY (MHz) 24.99 FREQUENCY (MHz) 24.99 1744 G36 1744 G37
U U U PI FU CTIO S SENSE (Pin 1):
Reference Sense Pin. Ground selects
MSBINV (Pin 22):
MSB Inversion Control. Low inverts ±1V. VDD selects ±1.6V. Greater than 1V and less than the MSB, 2’s complement output format. High does not 1.6V applied to the SENSE pin selects an input range of invert the MSB, offset binary output format. ±VSENSE, ±1.6V is the largest valid input range.
ENC (Pin 23):
Encode Input. The input sample starts on
VCM (Pin 2):
2.5V Output and Input Common Mode Bias. the positive edge. Bypass to ground with 4.7µF ceramic chip capacitor.
ENC (Pin 24):
Encode Complement Input. Conversion
GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37):
ADC starts on the negative edge. Bypass to ground with 0.1µF Power Ground. ceramic for single-ended encode signal.
A + IN (Pin 4):
Positive Differential Analog Input.
OE (Pin 25):
Output Enable. Low enables outputs. Logic
A –
high makes outputs Hi-Z.
IN (Pin 5):
Negative Differential Analog Input.
V CLKOUT (Pin 26):
Data Valid Output. Latch data on the
DD (Pins 7, 8, 17, 18, 20):
5V Supply. Bypass to AGND with 1µF ceramic chip capacitor. rising edge of CLKOUT.
REFLB (Pin 10):
ADC Low Reference. Bypass to Pin 11 with
OGND (Pins 27, 38, 47):
Output Driver Ground. 0.1µF ceramic chip capacitor. Do not connect to Pin␣ 14.
D0-D3 (Pins 28 to 31):
Digital Outputs. D0 is the LSB.
REFHA (Pin 11):
ADC High Reference. Bypass to Pin 10 with
OVDD (Pins 32, 43):
Positive Supply for the Output Driv- 0.1µF ceramic chip capacitor, to Pin 14 with a 4.7µF ceramic ers. Bypass to ground with 0.1µF ceramic chip capacitor. capacitor and to ground with 1µF ceramic capacitor.
D4-D6 (Pins 33 to 35):
Digital Outputs.
REFLA (Pin 14):
ADC Low Reference. Bypass to Pin 15 with
D7-D10 (Pins 39 to 42):
Digital Outputs. 0.1µF ceramic chip capacitor, to Pin 11 with a 4.7µF ceramic
D11-D13 (Pins 44 to 46):
Digital Outputs. D13 is the MSB. capacitor and to ground with 1µF ceramic capacitor.
OF (Pin 48):
Over/Under Flow Output. High when an over
REFHB (Pin 15):
ADC High Reference. Bypass to Pin 14 with or under flow has occurred. 0.1µF ceramic chip capacitor. Do not connect to Pin␣ 11. 1744f 9
