Datasheet LTC2123 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual 14-Bit 250Msps ADC with JESD204B Serial Outputs |
| Pages / Page | 50 / 10 — PIN FUNCTIONS VDD (Pins 1, 12, 13, 23, 24, 37, 38, 48):. GND (Pins 2, 8, … |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
PIN FUNCTIONS VDD (Pins 1, 12, 13, 23, 24, 37, 38, 48):. GND (Pins 2, 8, 11, 14, 17, 20, 39, 40, 47, Exposed Pad
Model Line for this Datasheet
Text Version of Document
LTC2123
PIN FUNCTIONS VDD (Pins 1, 12, 13, 23, 24, 37, 38, 48):
1.8V Power In subclass 2 a low to high transition of SYNC~ is sampled Supply. Bypass to ground with 0.1µF ceramic capacitors. on the rising edge of DEVCLK to reset the internal dividers Adjacent pins can share bypass capacitor. and set up deterministic latency.
GND (Pins 2, 8, 11, 14, 17, 20, 39, 40, 47, Exposed Pad OVDD (Pins 25, 26, 35, 36):
1.2V to 1.9V Output Driver
Pin 49):
Device Power Ground. The exposed pad must be Supply. Bypass each pair to ground with 0.1μF ceramic soldered to the PCB ground. capacitors.
A + – INA /AINA (Pins 3, 4):
Analog Input Pair for Channel A.
CMLOUT_B1–/CMLOUT_B1+ (Pins 27, 28):
Current Mode
SENSE (Pin 5):
Reference Programming Pin. Connecting Logic Output Pair for Channel B Lane 2. Must be terminated SENSE to V with a 50Ω resistor to OVDD, a differential 100Ω resistor DD selects the internal reference and a ±0.75V input range. An external reference between 1.2V and 1.3V to the complementary output, or AC coupled to another applied to SENSE selects an input range of ±0.6 • V termination voltage. SENSE.
V CMLOUT_B0–/CMLOUT_B0+ (Pins 29, 30):
Current Mode
REF (Pin 6):
Reference Voltage Output. Bypass to ground with a 2.2μF ceramic capacitor. Nominally 1.25V. Logic Output Pair for Channel B Lane 1. Must be terminated with a 50Ω resistor to OVDD, a differential 100Ω resistor
VCM (Pin 7):
Common Mode Bias Output. Nominally equal to the complementary output, or AC coupled to another to 0.435 • VDD. VCM should be used to bias the common termination voltage. mode of the analog inputs. Bypass to ground with a 0.1μF ceramic capacitor.
CMLOUT_A0–/CMLOUT_A0+ (Pins 31, 32):
Current Mode Logic Output Pair for Channel A Lane 1. Must be terminated
A – + INB /AINB (Pins 9, 10):
Analog Input Pair for Channel B. with a 50Ω resistor to OVDD, a differential 100Ω resistor
DEVCLK–/DEVCLK+ (Pins 15, 16):
Device Clock Input Pair. The to the complementary output, or AC coupled to another sample clock is derived from this differential signal. An inter- termination voltage. nal DEVCLK divider may be programmed through the SPI to
CMLOUT_A1–/CMLOUT_A1+ (Pins 33, 34):
Current Mode either divide by one or two (DEVCLK = DEVCLK+ – DEVCLK–). Logic Output Pair for Channel A Lane 2. Must be terminated with a 50Ω resistor to OV In divide-by-one mode, the analog signal is sampled on DD, a differential 100Ω resistor to the complementary output, or AC coupled to another the falling edge of DEVCLK. termination voltage. In divide-by-two mode, the analog signal is sampled once
OF–/OF+ (Pins 41, 42):
Over/Underflow LVDS Digital every two DEVCLK cycles on the rising edge of DEVCLK. Output. OF is high when an overflow or underflow has The actual sampling cycle is established at the time of the occurred. The overflows for channel A and channel B are clock divider initialization. In subclass 1, a low-to-high tran- multiplexed together and transmitted at twice the sample sition of the SYSREF signal will initialize the divide-by-two frequency (OF = OF+ – OF–). circuit on the first rising edge of DEVCLK. In subclass 2, a low to high transition of the SYNC~ signal will initialize the
SDO (Pin 43):
Serial Interface Data Output. SDO is the divide-by-two circuit on the first rising edge of DEVCLK. optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched
SYSREF+/SYSREF– (Pins 18, 19):
A JESD204B Subclass 1 on the falling edge of SCK. SDO is an open-drain N-channel Input Signal Pair. A low to high transition of SYSREF is sampled MOSFET output that requires an external 2k pull-up resis- on the rising edge of DEVCLK to reset the internal dividers and tor from 1.8V to 3.3V. If readback from the mode control set up deterministic latency (SYSREF = SYSREF+ – SYSREF–). registers is not needed, the pull-up resistor is not neces-
SYNC~+/SYNC~– (Pins 21, 22):
A JESD204B Synchro- sary and SDO can be left unconnected. nization Input Signal Pair. Used to establish initial Code Group synchronization for all three subclasses. A low level of the SYNC~ signal causes the LTC2123 to output K28.5 commas (SYNC~ = SYNC~+ – SYNC~–). 2123fc 10 For more information www.linear.com/LTC2123 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Converter Characteristics Pin Configuration Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs and Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram SPI Timing Definitions Applications Information Typical Applications Package Description Typical Application Related Parts
PIN FUNCTIONS VDD (Pins 1, 12, 13, 23, 24, 37, 38, 48):
1.8V Power In subclass 2 a low to high transition of SYNC~ is sampled Supply. Bypass to ground with 0.1µF ceramic capacitors. on the rising edge of DEVCLK to reset the internal dividers Adjacent pins can share bypass capacitor. and set up deterministic latency.
GND (Pins 2, 8, 11, 14, 17, 20, 39, 40, 47, Exposed Pad OVDD (Pins 25, 26, 35, 36):
1.2V to 1.9V Output Driver
Pin 49):
Device Power Ground. The exposed pad must be Supply. Bypass each pair to ground with 0.1μF ceramic soldered to the PCB ground. capacitors.
A + – INA /AINA (Pins 3, 4):
Analog Input Pair for Channel A.
CMLOUT_B1–/CMLOUT_B1+ (Pins 27, 28):
Current Mode
SENSE (Pin 5):
Reference Programming Pin. Connecting Logic Output Pair for Channel B Lane 2. Must be terminated SENSE to V with a 50Ω resistor to OVDD, a differential 100Ω resistor DD selects the internal reference and a ±0.75V input range. An external reference between 1.2V and 1.3V to the complementary output, or AC coupled to another applied to SENSE selects an input range of ±0.6 • V termination voltage. SENSE.
V CMLOUT_B0–/CMLOUT_B0+ (Pins 29, 30):
Current Mode
REF (Pin 6):
Reference Voltage Output. Bypass to ground with a 2.2μF ceramic capacitor. Nominally 1.25V. Logic Output Pair for Channel B Lane 1. Must be terminated with a 50Ω resistor to OVDD, a differential 100Ω resistor
VCM (Pin 7):
Common Mode Bias Output. Nominally equal to the complementary output, or AC coupled to another to 0.435 • VDD. VCM should be used to bias the common termination voltage. mode of the analog inputs. Bypass to ground with a 0.1μF ceramic capacitor.
CMLOUT_A0–/CMLOUT_A0+ (Pins 31, 32):
Current Mode Logic Output Pair for Channel A Lane 1. Must be terminated
A – + INB /AINB (Pins 9, 10):
Analog Input Pair for Channel B. with a 50Ω resistor to OVDD, a differential 100Ω resistor
DEVCLK–/DEVCLK+ (Pins 15, 16):
Device Clock Input Pair. The to the complementary output, or AC coupled to another sample clock is derived from this differential signal. An inter- termination voltage. nal DEVCLK divider may be programmed through the SPI to
CMLOUT_A1–/CMLOUT_A1+ (Pins 33, 34):
Current Mode either divide by one or two (DEVCLK = DEVCLK+ – DEVCLK–). Logic Output Pair for Channel A Lane 2. Must be terminated with a 50Ω resistor to OV In divide-by-one mode, the analog signal is sampled on DD, a differential 100Ω resistor to the complementary output, or AC coupled to another the falling edge of DEVCLK. termination voltage. In divide-by-two mode, the analog signal is sampled once
OF–/OF+ (Pins 41, 42):
Over/Underflow LVDS Digital every two DEVCLK cycles on the rising edge of DEVCLK. Output. OF is high when an overflow or underflow has The actual sampling cycle is established at the time of the occurred. The overflows for channel A and channel B are clock divider initialization. In subclass 1, a low-to-high tran- multiplexed together and transmitted at twice the sample sition of the SYSREF signal will initialize the divide-by-two frequency (OF = OF+ – OF–). circuit on the first rising edge of DEVCLK. In subclass 2, a low to high transition of the SYNC~ signal will initialize the
SDO (Pin 43):
Serial Interface Data Output. SDO is the divide-by-two circuit on the first rising edge of DEVCLK. optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched
SYSREF+/SYSREF– (Pins 18, 19):
A JESD204B Subclass 1 on the falling edge of SCK. SDO is an open-drain N-channel Input Signal Pair. A low to high transition of SYSREF is sampled MOSFET output that requires an external 2k pull-up resis- on the rising edge of DEVCLK to reset the internal dividers and tor from 1.8V to 3.3V. If readback from the mode control set up deterministic latency (SYSREF = SYSREF+ – SYSREF–). registers is not needed, the pull-up resistor is not neces-
SYNC~+/SYNC~– (Pins 21, 22):
A JESD204B Synchro- sary and SDO can be left unconnected. nization Input Signal Pair. Used to establish initial Code Group synchronization for all three subclasses. A low level of the SYNC~ signal causes the LTC2123 to output K28.5 commas (SYNC~ = SYNC~+ – SYNC~–). 2123fc 10 For more information www.linear.com/LTC2123 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Converter Characteristics Pin Configuration Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs and Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram SPI Timing Definitions Applications Information Typical Applications Package Description Typical Application Related Parts
