Datasheet LTC2142-12, LTC2141-12, LTC2140-12 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | 12-Bit, 65Msps Low Power Dual ADCs |
| Pages / Page | 38 / 1 — FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. 2-Tone FFT, fIN … |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. 2-Tone FFT, fIN = 70MHz and 69MHz
Model Line for this Datasheet
- LTC2140CUP-12#PBF LTC2140CUP-12#PBF LTC2140CUP-12#TRPBF LTC2140CUP-12#TRPBF LTC2140IUP-12#PBF LTC2140IUP-12#PBF LTC2140IUP-12#TRPBF LTC2140IUP-12#TRPBF
Text Version of Document
LTC2142-12/ LTC2141-12/LTC2140-12 12-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs
FEATURES DESCRIPTION
n 2-Channel Simultaneously Sampling ADC The LTC®2142-12/LTC2141-12/LTC2140-12 are 2-channel n 70.8dB SNR simultaneous sampling 12-bit A/D converters designed n 89dB SFDR for digitizing high frequency, wide dynamic range signals. n Low Power: 92mW/65mW/48mW Total They are perfect for demanding communications applica- 46mW/33mW/24mW per Channel tions with AC performance that includes 70.8dB SNR and n Single 1.8V Supply 89dB spurious free dynamic range (SFDR). Ultralow jitter n CMOS, DDR CMOS, or DDR LVDS Outputs of 0.08psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 750MHz Full Power Bandwidth S/H DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ) n Optional Data Output Randomizer and no missing codes over temperature. The transition n Optional Clock Duty Cycle Stabilizer noise is 0.3LSB n Shutdown and Nap Modes RMS. n Serial SPI Port for Configuration The digital outputs can be either full rate CMOS, double n 64-Pin (9mm × 9mm) QFN Package data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to
APPLICATIONS
range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differentially n Communications or single-ended with a sine wave, PECL, LVDS, TTL, or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Software Defined Radios lows high performance at full speed for a wide range of n Portable Medical Imaging clock duty cycles. n Multi-Channel Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Nondestructive Testing Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V 1.8V
2-Tone FFT, fIN = 70MHz and 69MHz
VDD OVDD 0 –10 –20 CH 1 12-BIT D1_11 ANALOG S/H –30 ADC CORE t INPUT t –40 CMOS, t D1_0 DDR CMOS –50 OR –60 D2_11 DDR LVDS –70 OUTPUT t OUTPUTS CH 2 t DRIVERS 12-BIT t AMPLITUDE (dBFS) –80 ANALOG S/H ADC CORE D2_0 INPUT –90 –100 –110 –120 65MHz CLOCK 0 10 20 30 CLOCK CONTROL FREQUENCY (MHz) FREQUENCY (MHz) 21821012 21821012 TA01b TA01b 21421012 TA01a GND OGND 21421012fa 1
FEATURES DESCRIPTION
n 2-Channel Simultaneously Sampling ADC The LTC®2142-12/LTC2141-12/LTC2140-12 are 2-channel n 70.8dB SNR simultaneous sampling 12-bit A/D converters designed n 89dB SFDR for digitizing high frequency, wide dynamic range signals. n Low Power: 92mW/65mW/48mW Total They are perfect for demanding communications applica- 46mW/33mW/24mW per Channel tions with AC performance that includes 70.8dB SNR and n Single 1.8V Supply 89dB spurious free dynamic range (SFDR). Ultralow jitter n CMOS, DDR CMOS, or DDR LVDS Outputs of 0.08psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 750MHz Full Power Bandwidth S/H DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ) n Optional Data Output Randomizer and no missing codes over temperature. The transition n Optional Clock Duty Cycle Stabilizer noise is 0.3LSB n Shutdown and Nap Modes RMS. n Serial SPI Port for Configuration The digital outputs can be either full rate CMOS, double n 64-Pin (9mm × 9mm) QFN Package data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to
APPLICATIONS
range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differentially n Communications or single-ended with a sine wave, PECL, LVDS, TTL, or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Software Defined Radios lows high performance at full speed for a wide range of n Portable Medical Imaging clock duty cycles. n Multi-Channel Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Nondestructive Testing Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V 1.8V
2-Tone FFT, fIN = 70MHz and 69MHz
VDD OVDD 0 –10 –20 CH 1 12-BIT D1_11 ANALOG S/H –30 ADC CORE t INPUT t –40 CMOS, t D1_0 DDR CMOS –50 OR –60 D2_11 DDR LVDS –70 OUTPUT t OUTPUTS CH 2 t DRIVERS 12-BIT t AMPLITUDE (dBFS) –80 ANALOG S/H ADC CORE D2_0 INPUT –90 –100 –110 –120 65MHz CLOCK 0 10 20 30 CLOCK CONTROL FREQUENCY (MHz) FREQUENCY (MHz) 21821012 21821012 TA01b TA01b 21421012 TA01a GND OGND 21421012fa 1
