Datasheet LTC2159 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 16-Bit, 20Msps Low Power ADC |
| Pages / Page | 32 / 8 — elecTrical characTerisTics. Note 1:. Note 6:. Note 7:. Note 2:. Note 3:. … |
| File Format / Size | PDF / 532 Kb |
| Document Language | English |
elecTrical characTerisTics. Note 1:. Note 6:. Note 7:. Note 2:. Note 3:. Note 8:. Note 9:. Note 4:. Note 10:. Note 5:. TiMing DiagraMs
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LTC2159
elecTrical characTerisTics Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute best fit straight line to the transfer curve. The deviation is measured from Maximum Rating condition for extended periods may affect device the center of the quantization band. reliability and lifetime.
Note 7:
Offset error is the offset voltage measured from –0.5 LSB when
Note 2:
All voltage values are with respect to GND with GND and OGND the output code flickers between 0000 0000 0000 0000 and 1111 1111 shorted (unless otherwise noted). 1111 1111 in 2’s complement output mode.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 8:
Guaranteed by design, not subject to test. will be clamped by internal diodes. This product can handle input currents
Note 9:
VDD = 1.8V, fSAMPLE = 20MHz, CMOS outputs, ENC+ = single- of greater than 100mA below GND or above VDD without latchup. ended 1.8V square wave, ENC– = 0V, input range = 2VP-P with differential
Note 4:
When these pin voltages are taken below GND they will be drive, 5pF load on each digital output unless otherwise noted. clamped by internal diodes. When these pin voltages are taken above VDD
Note 10:
Recommended operating conditions. they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup.
Note 5:
VDD = OVDD = 1.8V, fSAMPLE = 20MHz, LVDS outputs, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted.
TiMing DiagraMs Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels
tAP ANALOG N N + 2 N + 4 INPUT N + 3 tH N + 1 tL ENC– ENC+ tD D0–D15, OF N – 6 N – 5 N – 4 N – 3 N – 2 tC CLKOUT+ CLKOUT– 2159 TD01 2159f 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
elecTrical characTerisTics Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute best fit straight line to the transfer curve. The deviation is measured from Maximum Rating condition for extended periods may affect device the center of the quantization band. reliability and lifetime.
Note 7:
Offset error is the offset voltage measured from –0.5 LSB when
Note 2:
All voltage values are with respect to GND with GND and OGND the output code flickers between 0000 0000 0000 0000 and 1111 1111 shorted (unless otherwise noted). 1111 1111 in 2’s complement output mode.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 8:
Guaranteed by design, not subject to test. will be clamped by internal diodes. This product can handle input currents
Note 9:
VDD = 1.8V, fSAMPLE = 20MHz, CMOS outputs, ENC+ = single- of greater than 100mA below GND or above VDD without latchup. ended 1.8V square wave, ENC– = 0V, input range = 2VP-P with differential
Note 4:
When these pin voltages are taken below GND they will be drive, 5pF load on each digital output unless otherwise noted. clamped by internal diodes. When these pin voltages are taken above VDD
Note 10:
Recommended operating conditions. they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup.
Note 5:
VDD = OVDD = 1.8V, fSAMPLE = 20MHz, LVDS outputs, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted.
TiMing DiagraMs Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels
tAP ANALOG N N + 2 N + 4 INPUT N + 3 tH N + 1 tL ENC– ENC+ tD D0–D15, OF N – 6 N – 5 N – 4 N – 3 N – 2 tC CLKOUT+ CLKOUT– 2159 TD01 2159f 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
