Datasheet LTC2205-14 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | 14-Bit, 65Msps ADC |
| Pages / Page | 28 / 1 — FEATURES. DESCRIPTION. Sample Rate: 65Msps. 78.3dB SNR and 98dB SFDR … |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
FEATURES. DESCRIPTION. Sample Rate: 65Msps. 78.3dB SNR and 98dB SFDR (2.25VP-P Range)
Model Line for this Datasheet
Text Version of Document
LTC2205-14 14-Bit, 65Msps ADC
FEATURES DESCRIPTION
n
Sample Rate: 65Msps
The LTC®2205-14 is a sampling 14-bit A/D converter n
78.3dB SNR and 98dB SFDR (2.25VP-P Range)
designed for digitizing high frequency, wide dynamic range n
SFDR >90dB at 140MHz (1.5VP-P Input Range)
signals up to input frequencies of 700MHz. The input range n
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
of the ADC can be optimized with the PGA front end. n
700MHz Full Power Bandwidth S/H
The LTC2205-14 is perfect for demanding communications n
Optional Internal Dither
applications, with AC performance that includes 78.3dB n
Optional Data Output Randomizer
SNR and 98dB spurious free dynamic range (SFDR). n Single 3.3V Supply Ultralow jitter of 90fsRMS allows undersampling of high n Power Dissipation: 600mW input frequencies with excellent noise performance. n Optional Clock Duty Cycle Stabilizer Maximum DC specs include ±1.5LSB INL, ±1LSB DNL n Out-of-Range Indicator (no missing codes). n Pin Compatible Family 105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit) A separate output power supply allows the CMOS output 80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit) swing to range from 0.5V to 3.6V. 65Msps: LTC2205 (16-Bit) The ENC+ and ENC– inputs may be driven differentially 40Msps: LTC2204 (16-Bit) or single-ended with a sine wave, PECL, LVDS, TTL or n 48-Pin (7mm × 7mm) QFN Package CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range
APPLICATIONS
of clock duty cycles. n Telecommunications , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE
TYPICAL APPLICATION
3.3V
LTC2205-14: 32K Point FFT,
SENSE
fIN = 5.1MHz, –1dBFS,
OVDD
PGA = 0, DITH = 0
1.25V INTERNAL ADC 0.5V TO 3.6V VCM COMMON MODE REFERENCE 0 0.1μF 2.2μF BIAS VOLTAGE GENERATOR –10 –20 OF AIN+ –30 + CLKOUT 14-BIT CORRECTION OUTPUT –40 D13 ANALOG S/H PIPELINED LOGIC AND DRIVERS • –50 INPUT AMP ADC CORE SHIFT REGISTER – • –60 AIN– • –70 D0 –80 OGND AMPLITUDE (dBFS) –90 CLOCK/DUTY –100 CYCLE V 3.3V DD –110 CONTROL 0.1μF 0.1μF –120 GND 0.1μF –130 220514 TA01 0 5 10 15 20 25 30 ENC ENC PGA SHDN DITH MODE OE RAND FREQUENCY (MHz) ADC CONTROL INPUTS 220514 G04 220514fb 1
FEATURES DESCRIPTION
n
Sample Rate: 65Msps
The LTC®2205-14 is a sampling 14-bit A/D converter n
78.3dB SNR and 98dB SFDR (2.25VP-P Range)
designed for digitizing high frequency, wide dynamic range n
SFDR >90dB at 140MHz (1.5VP-P Input Range)
signals up to input frequencies of 700MHz. The input range n
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
of the ADC can be optimized with the PGA front end. n
700MHz Full Power Bandwidth S/H
The LTC2205-14 is perfect for demanding communications n
Optional Internal Dither
applications, with AC performance that includes 78.3dB n
Optional Data Output Randomizer
SNR and 98dB spurious free dynamic range (SFDR). n Single 3.3V Supply Ultralow jitter of 90fsRMS allows undersampling of high n Power Dissipation: 600mW input frequencies with excellent noise performance. n Optional Clock Duty Cycle Stabilizer Maximum DC specs include ±1.5LSB INL, ±1LSB DNL n Out-of-Range Indicator (no missing codes). n Pin Compatible Family 105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit) A separate output power supply allows the CMOS output 80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit) swing to range from 0.5V to 3.6V. 65Msps: LTC2205 (16-Bit) The ENC+ and ENC– inputs may be driven differentially 40Msps: LTC2204 (16-Bit) or single-ended with a sine wave, PECL, LVDS, TTL or n 48-Pin (7mm × 7mm) QFN Package CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range
APPLICATIONS
of clock duty cycles. n Telecommunications , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE
TYPICAL APPLICATION
3.3V
LTC2205-14: 32K Point FFT,
SENSE
fIN = 5.1MHz, –1dBFS,
OVDD
PGA = 0, DITH = 0
1.25V INTERNAL ADC 0.5V TO 3.6V VCM COMMON MODE REFERENCE 0 0.1μF 2.2μF BIAS VOLTAGE GENERATOR –10 –20 OF AIN+ –30 + CLKOUT 14-BIT CORRECTION OUTPUT –40 D13 ANALOG S/H PIPELINED LOGIC AND DRIVERS • –50 INPUT AMP ADC CORE SHIFT REGISTER – • –60 AIN– • –70 D0 –80 OGND AMPLITUDE (dBFS) –90 CLOCK/DUTY –100 CYCLE V 3.3V DD –110 CONTROL 0.1μF 0.1μF –120 GND 0.1μF –130 220514 TA01 0 5 10 15 20 25 30 ENC ENC PGA SHDN DITH MODE OE RAND FREQUENCY (MHz) ADC CONTROL INPUTS 220514 G04 220514fb 1
