Datasheet LTC2225 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 12-Bit, 10Msps Low Power 3V ADC |
| Pages / Page | 20 / 7 — TYPICAL PERFOR A CE CHARACTERISTICS. VDD vs Sample Rate,. OVDD vs Sample … |
| File Format / Size | PDF / 528 Kb |
| Document Language | English |
TYPICAL PERFOR A CE CHARACTERISTICS. VDD vs Sample Rate,. OVDD vs Sample Rate, 5MHz Sine. 5MHz Sine Wave Input, –1dB
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LTC2225
W U TYPICAL PERFOR A CE CHARACTERISTICS I I VDD vs Sample Rate, OVDD vs Sample Rate, 5MHz Sine 5MHz Sine Wave Input, –1dB Wave Input, –1dB, OVDD = 1.8V
25 1.0 0.9 2V RANGE 0.8 0.7 20 0.6 1V RANGE (mA) (mA) 0.5 I VDD I OVDD 0.4 15 0.3 0.2 0.1 10 0 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 SAMPLE RATE (Msps) SAMPLE RATE (Msps) 2225 G12 2225 G13
U U U PI FU CTIO S AIN+ (Pin 1):
Positive Differential Analog Input. OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to V
A
DD and OE to VDD
IN- (Pin 2):
Negative Differential Analog Input. results in sleep mode with the outputs at high impedance.
REFH (Pins 3, 4):
ADC High Reference. Short together and
OE (Pin 11):
Output Enable Pin. Refer to SHDN pin bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as function. close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground
NC (Pins 12, 13):
Do Not Connect These Pins. with a 1µF ceramic chip capacitor.
D0 – D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, REFL (Pins 5, 6):
ADC Low Reference. Short together and
27):
Digital Outputs. D11 is the MSB. bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 3, 4 with
OGND (Pin 20):
Output Driver Ground. an additional 2.2µF ceramic chip capacitor and to ground
OVDD (Pin 21):
Positive Supply for the Output Drivers. with a 1µF ceramic chip capacitor. Bypass to ground with 0.1µF ceramic chip capacitor.
VDD (Pins 7, 32):
3V Supply. Bypass to GND with 0.1µF
OF (Pin 28):
Over/Under Flow Output. High when an over ceramic chip capacitors. or under flow has occurred.
GND (Pin 8):
ADC Power Ground.
MODE (Pin 29):
Output Format and Clock Duty Cycle
CLK (Pin 9):
Clock Input. The input sample starts on the Stabilizer Selection Pin. Connecting MODE to GND selects positive edge. offset binary output format and turns the clock duty cycle stabilizer off. 1/3 V
SHDN (Pin 10):
Shutdown Mode Selection Pin. Connect- DD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 V ing SHDN to GND and OE to GND results in normal DD selects 2’s complement output format and turns the clock duty operation with the outputs enabled. Connecting SHDN to cycle stabilizer on. V GND and OE to V DD selects 2’s complement output DD results in normal operation with the outputs at high impedance. Connecting SHDN to V format and turns the clock duty cycle stabilizer off. DD and 2225fa 7
W U TYPICAL PERFOR A CE CHARACTERISTICS I I VDD vs Sample Rate, OVDD vs Sample Rate, 5MHz Sine 5MHz Sine Wave Input, –1dB Wave Input, –1dB, OVDD = 1.8V
25 1.0 0.9 2V RANGE 0.8 0.7 20 0.6 1V RANGE (mA) (mA) 0.5 I VDD I OVDD 0.4 15 0.3 0.2 0.1 10 0 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 SAMPLE RATE (Msps) SAMPLE RATE (Msps) 2225 G12 2225 G13
U U U PI FU CTIO S AIN+ (Pin 1):
Positive Differential Analog Input. OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to V
A
DD and OE to VDD
IN- (Pin 2):
Negative Differential Analog Input. results in sleep mode with the outputs at high impedance.
REFH (Pins 3, 4):
ADC High Reference. Short together and
OE (Pin 11):
Output Enable Pin. Refer to SHDN pin bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as function. close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground
NC (Pins 12, 13):
Do Not Connect These Pins. with a 1µF ceramic chip capacitor.
D0 – D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, REFL (Pins 5, 6):
ADC Low Reference. Short together and
27):
Digital Outputs. D11 is the MSB. bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 3, 4 with
OGND (Pin 20):
Output Driver Ground. an additional 2.2µF ceramic chip capacitor and to ground
OVDD (Pin 21):
Positive Supply for the Output Drivers. with a 1µF ceramic chip capacitor. Bypass to ground with 0.1µF ceramic chip capacitor.
VDD (Pins 7, 32):
3V Supply. Bypass to GND with 0.1µF
OF (Pin 28):
Over/Under Flow Output. High when an over ceramic chip capacitors. or under flow has occurred.
GND (Pin 8):
ADC Power Ground.
MODE (Pin 29):
Output Format and Clock Duty Cycle
CLK (Pin 9):
Clock Input. The input sample starts on the Stabilizer Selection Pin. Connecting MODE to GND selects positive edge. offset binary output format and turns the clock duty cycle stabilizer off. 1/3 V
SHDN (Pin 10):
Shutdown Mode Selection Pin. Connect- DD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 V ing SHDN to GND and OE to GND results in normal DD selects 2’s complement output format and turns the clock duty operation with the outputs enabled. Connecting SHDN to cycle stabilizer on. V GND and OE to V DD selects 2’s complement output DD results in normal operation with the outputs at high impedance. Connecting SHDN to V format and turns the clock duty cycle stabilizer off. DD and 2225fa 7
