Datasheet LTC2232, LTC2233 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | 10-Bit, 80Msps ADCs |
| Pages / Page | 28 / 1 — FEATURES. DESCRIPTIO. Sample Rate: 105Msps/80Msps. 61dB SNR up to 140MHz … |
| File Format / Size | PDF / 865 Kb |
| Document Language | English |
FEATURES. DESCRIPTIO. Sample Rate: 105Msps/80Msps. 61dB SNR up to 140MHz Input. 75dB SFDR up to 200MHz Input
Model Line for this Datasheet
Text Version of Document
LTC2232/LTC2233 10-Bit,105Msps/ 80Msps ADCs
U FEATURES DESCRIPTIO
■
Sample Rate: 105Msps/80Msps
The LTC®2232 and LTC2233 are 105Msps/80Msps, sam- ■
61dB SNR up to 140MHz Input
pling 10-bit A/D converters designed for digitizing high ■
75dB SFDR up to 200MHz Input
frequency, wide dynamic range signals. The LTC2232/ ■
775MHz Full Power Bandwidth S/H
LTC2233 are perfect for demanding communications ■
Single 3.3V Supply
applications with AC performance that includes 61dB SNR ■
Low Power Dissipation: 475mW/366mW
and 75dB spurious free dynamic range for signals ■ Selectable Input Ranges: ±0.5V or ±1V up to 200MHz. Ultralow jitter of 0.15psRMS allows ■ No Missing Codes undersampling of IF frequencies with excellent noise ■ Optional Clock Duty Cycle Stabilizer performance. ■ Shutdown and Nap Modes DC specs include ±0.15LSB INL (typ), ±0.1LSB DNL (typ) ■ Data Ready Output Clock and ±0.8LSB INL, ±0.6LSB DNL over temperature. The ■ Pin Compatible Family transition noise is a low 0.12LSB 135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit) RMS. 105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit) A separate output power supply allows the outputs to drive 80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit) 0.5V to 3.6V logic. ■ 48-Pin 7mm x 7mm QFN Package
U
The ENC+ and ENC– inputs may be driven differentially or
APPLICATIO S
single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high ■ Wireless and Wired Broadband Communication performance at full speed for a wide range of clock duty ■ Cable Head-End Systems cycles. ■ Power Amplifier Linearization ■ Communications Test Equipment , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
U TYPICAL APPLICATIO
3.3V VDD
SFDR vs Input Frequency
0.5V 90 TO 3.6V REFH FLEXIBLE REFL REFERENCE 85 OVDD 4th OR HIGHER 80 + D9 75 10-BIT • ANALOG INPUT CORRECTION OUTPUT PIPELINED • 70 INPUT S/H LOGIC DRIVERS ADC CORE • 2nd OR 3rd – D0 SFDR (dBFS) 65 60 OGND 55 CLOCK/DUTY CYCLE 50 CONTROL 0 100 200 300 400 500 600 INPUT FREQUENCY (MHz) 22323 TA01b 22323 TA01 ENCODE INPUT 22323fa 1
U FEATURES DESCRIPTIO
■
Sample Rate: 105Msps/80Msps
The LTC®2232 and LTC2233 are 105Msps/80Msps, sam- ■
61dB SNR up to 140MHz Input
pling 10-bit A/D converters designed for digitizing high ■
75dB SFDR up to 200MHz Input
frequency, wide dynamic range signals. The LTC2232/ ■
775MHz Full Power Bandwidth S/H
LTC2233 are perfect for demanding communications ■
Single 3.3V Supply
applications with AC performance that includes 61dB SNR ■
Low Power Dissipation: 475mW/366mW
and 75dB spurious free dynamic range for signals ■ Selectable Input Ranges: ±0.5V or ±1V up to 200MHz. Ultralow jitter of 0.15psRMS allows ■ No Missing Codes undersampling of IF frequencies with excellent noise ■ Optional Clock Duty Cycle Stabilizer performance. ■ Shutdown and Nap Modes DC specs include ±0.15LSB INL (typ), ±0.1LSB DNL (typ) ■ Data Ready Output Clock and ±0.8LSB INL, ±0.6LSB DNL over temperature. The ■ Pin Compatible Family transition noise is a low 0.12LSB 135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit) RMS. 105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit) A separate output power supply allows the outputs to drive 80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit) 0.5V to 3.6V logic. ■ 48-Pin 7mm x 7mm QFN Package
U
The ENC+ and ENC– inputs may be driven differentially or
APPLICATIO S
single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high ■ Wireless and Wired Broadband Communication performance at full speed for a wide range of clock duty ■ Cable Head-End Systems cycles. ■ Power Amplifier Linearization ■ Communications Test Equipment , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
U TYPICAL APPLICATIO
3.3V VDD
SFDR vs Input Frequency
0.5V 90 TO 3.6V REFH FLEXIBLE REFL REFERENCE 85 OVDD 4th OR HIGHER 80 + D9 75 10-BIT • ANALOG INPUT CORRECTION OUTPUT PIPELINED • 70 INPUT S/H LOGIC DRIVERS ADC CORE • 2nd OR 3rd – D0 SFDR (dBFS) 65 60 OGND 55 CLOCK/DUTY CYCLE 50 CONTROL 0 100 200 300 400 500 600 INPUT FREQUENCY (MHz) 22323 TA01b 22323 TA01 ENCODE INPUT 22323fa 1
