Datasheet LTC2240-12 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 12-Bit, 170Msps ADC |
| Pages / Page | 30 / 9 — PIN FUNCTIONS. (CMOS Mode). OFB (Pin 37):. A +. IN (Pins 1, 2):. A –. IN … |
| File Format / Size | PDF / 555 Kb |
| Document Language | English |
PIN FUNCTIONS. (CMOS Mode). OFB (Pin 37):. A +. IN (Pins 1, 2):. A –. IN (Pins 3, 4):. CLKOUTB (Pin 38):. REFHA (Pins 5, 6):
Model Line for this Datasheet
Text Version of Document
LTC2240-12
PIN FUNCTIONS (CMOS Mode) OFB (Pin 37):
Over/Under Flow Output for B Bus. High
A +
when an over or under fl ow has occurred. At high imped-
IN (Pins 1, 2):
Positive Differential Analog Input. ance in full rate CMOS mode.
A – IN (Pins 3, 4):
Negative Differential Analog Input.
CLKOUTB (Pin 38):
Data Valid Output for B Bus. In demux
REFHA (Pins 5, 6):
ADC High Reference. Bypass to mode with interleaved update, latch B bus data on the fall- Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11, ing edge of CLKOUTB. In demux mode with simultaneous 12 with a 2.2μF ceramic capacitor and to ground with 1μF update, latch B bus data on the rising edge of CLKOUTB. ceramic capacitor. This pin does not become high impedance in full rate
REFLB (Pins 7, 8):
ADC Low Reference. Bypass to Pins CMOS mode. 5, 6 with 0.1μF ceramic chip capacitor. Do not connect to
CLKOUTA (Pin 39):
Data Valid Output for A Bus. Latch A Pins 11, 12. bus data on the falling edge of CLKOUTA.
REFHB (Pins 9, 10):
ADC High Reference. Bypass to
DA0 - DA11 (Pins 40, 43, 44, 45, 46, 47, 48, 51, 52, 53,
Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not
54, 55):
Digital Outputs, A Bus. DA11 is the MSB. connect to Pins 5, 6.
OFA (Pin 56):
Over/Under Flow Output for A Bus. High
REFLA (Pins 11, 12):
ADC Low Reference. Bypass to when an over or under fl ow has occurred. Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5, 6 with a 2.2μF ceramic capacitor and to ground with 1μF
LVDS (Pin 57):
Output Mode Selection Pin. Connecting ceramic capacitor. LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous
VDD (Pins 13, 14, 15, 62, 63):
2.5V Supply. Bypass to update. Connecting LVDS to 2/3VDD selects demux CMOS GND with 0.1μF ceramic chip capacitors. mode with interleaved update. Connecting LVDS to VDD
GND (Pins 16, 61, 64):
ADC Power Ground. selects LVDS mode.
ENC+ (Pin 17):
Encode Input. Conversion starts on the
MODE (Pin 58):
Output Format and Clock Duty Cycle positive edge. Stabilizer Selection Pin. Connecting MODE to 0V selects
ENC– (Pin 18):
Encode Complement Input. Conversion offset binary output format and turns the clock duty cycle starts on the negative edge. Bypass to ground with 0.1μF stabilizer off. Connecting MODE to 1/3VDD selects offset ceramic for single-ended encode signal. binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3V
SHDN (Pin 19):
Shutdown Mode Selection Pin. Connecting DD selects 2’s complement output format and turns the clock duty cycle stabilizer on. SHDN to GND and OE to GND results in normal operation Connecting MODE to V with the outputs enabled. Connecting SHDN to GND and DD selects 2’s complement output OE format and turns the clock duty cycle stabilizer off. to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to V
SENSE (Pin 59):
Reference Programming Pin. Connecting DD and OE to GND results in nap mode with the outputs at high impedance. SENSE to VCM selects the internal reference and a ±0.5V Connecting SHDN to V input range. Connecting SENSE to V DD and OE to VDD results in sleep DD selects the internal mode with the outputs at high impedance. reference and a ±1V input range. An external reference
OE
greater than 0.5V and less than 1V applied to SENSE
(Pin 20):
Output Enable Pin. Refer to SHDN pin function. selects an input range of ±VSENSE. ±1V is the largest valid
DB0 - DB11 (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31,
input range.
32, 35, 36):
Digital Outputs, B Bus. DB11 is the MSB. At
V
high impedance in full rate CMOS mode.
CM (Pin 60):
1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2μF ceramic chip capacitor.
OGND (Pins 25, 33, 41, 50):
Output Driver Ground.
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The
OVDD (Pins 26, 34, 42, 49):
Positive Supply for the exposed pad on the bottom of the package needs to be Output Drivers. Bypass to ground with 0.1μF ceramic chip soldered to ground. capacitor. 224012fd 9 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS TIMING CHARACTERISTICS ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAMS APPLICATIONS INFORMATION PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS
PIN FUNCTIONS (CMOS Mode) OFB (Pin 37):
Over/Under Flow Output for B Bus. High
A +
when an over or under fl ow has occurred. At high imped-
IN (Pins 1, 2):
Positive Differential Analog Input. ance in full rate CMOS mode.
A – IN (Pins 3, 4):
Negative Differential Analog Input.
CLKOUTB (Pin 38):
Data Valid Output for B Bus. In demux
REFHA (Pins 5, 6):
ADC High Reference. Bypass to mode with interleaved update, latch B bus data on the fall- Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11, ing edge of CLKOUTB. In demux mode with simultaneous 12 with a 2.2μF ceramic capacitor and to ground with 1μF update, latch B bus data on the rising edge of CLKOUTB. ceramic capacitor. This pin does not become high impedance in full rate
REFLB (Pins 7, 8):
ADC Low Reference. Bypass to Pins CMOS mode. 5, 6 with 0.1μF ceramic chip capacitor. Do not connect to
CLKOUTA (Pin 39):
Data Valid Output for A Bus. Latch A Pins 11, 12. bus data on the falling edge of CLKOUTA.
REFHB (Pins 9, 10):
ADC High Reference. Bypass to
DA0 - DA11 (Pins 40, 43, 44, 45, 46, 47, 48, 51, 52, 53,
Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not
54, 55):
Digital Outputs, A Bus. DA11 is the MSB. connect to Pins 5, 6.
OFA (Pin 56):
Over/Under Flow Output for A Bus. High
REFLA (Pins 11, 12):
ADC Low Reference. Bypass to when an over or under fl ow has occurred. Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5, 6 with a 2.2μF ceramic capacitor and to ground with 1μF
LVDS (Pin 57):
Output Mode Selection Pin. Connecting ceramic capacitor. LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous
VDD (Pins 13, 14, 15, 62, 63):
2.5V Supply. Bypass to update. Connecting LVDS to 2/3VDD selects demux CMOS GND with 0.1μF ceramic chip capacitors. mode with interleaved update. Connecting LVDS to VDD
GND (Pins 16, 61, 64):
ADC Power Ground. selects LVDS mode.
ENC+ (Pin 17):
Encode Input. Conversion starts on the
MODE (Pin 58):
Output Format and Clock Duty Cycle positive edge. Stabilizer Selection Pin. Connecting MODE to 0V selects
ENC– (Pin 18):
Encode Complement Input. Conversion offset binary output format and turns the clock duty cycle starts on the negative edge. Bypass to ground with 0.1μF stabilizer off. Connecting MODE to 1/3VDD selects offset ceramic for single-ended encode signal. binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3V
SHDN (Pin 19):
Shutdown Mode Selection Pin. Connecting DD selects 2’s complement output format and turns the clock duty cycle stabilizer on. SHDN to GND and OE to GND results in normal operation Connecting MODE to V with the outputs enabled. Connecting SHDN to GND and DD selects 2’s complement output OE format and turns the clock duty cycle stabilizer off. to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to V
SENSE (Pin 59):
Reference Programming Pin. Connecting DD and OE to GND results in nap mode with the outputs at high impedance. SENSE to VCM selects the internal reference and a ±0.5V Connecting SHDN to V input range. Connecting SENSE to V DD and OE to VDD results in sleep DD selects the internal mode with the outputs at high impedance. reference and a ±1V input range. An external reference
OE
greater than 0.5V and less than 1V applied to SENSE
(Pin 20):
Output Enable Pin. Refer to SHDN pin function. selects an input range of ±VSENSE. ±1V is the largest valid
DB0 - DB11 (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31,
input range.
32, 35, 36):
Digital Outputs, B Bus. DB11 is the MSB. At
V
high impedance in full rate CMOS mode.
CM (Pin 60):
1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2μF ceramic chip capacitor.
OGND (Pins 25, 33, 41, 50):
Output Driver Ground.
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The
OVDD (Pins 26, 34, 42, 49):
Positive Supply for the exposed pad on the bottom of the package needs to be Output Drivers. Bypass to ground with 0.1μF ceramic chip soldered to ground. capacitor. 224012fd 9 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS TIMING CHARACTERISTICS ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAMS APPLICATIONS INFORMATION PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS
