Datasheet LTC2242-12 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 12-Bit, 250Msps ADC |
| Pages / Page | 30 / 10 — PIN FUNCTIONS. (LVDS Mode). OGND (Pins 25, 33, 41, 50):. AIN+ (Pins 1, … |
| File Format / Size | PDF / 486 Kb |
| Document Language | English |
PIN FUNCTIONS. (LVDS Mode). OGND (Pins 25, 33, 41, 50):. AIN+ (Pins 1, 2):. OVDD (Pins 26, 34, 42, 49):. AIN– (Pins 3, 4):
Model Line for this Datasheet
Text Version of Document
LTC2242-12
PIN FUNCTIONS (LVDS Mode) OGND (Pins 25, 33, 41, 50):
Output Driver Ground.
AIN+ (Pins 1, 2):
Positive Differential Analog Input.
OVDD (Pins 26, 34, 42, 49):
Positive Supply for the Out-
AIN– (Pins 3, 4):
Negative Differential Analog Input. put Drivers. Bypass to ground with 0.1μF ceramic chip capacitor.
REFHA (Pins 5, 6):
ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11,
CLKOUT–/CLKOUT+ (Pins 35 to 36):
LVDS Data Valid 12 with a 2.2μF ceramic capacitor and to ground with 1μF Output. Latch data on rising edge of CLKOUT–, falling ceramic capacitor. edge of CLKOUT+.
REFLB (Pins 7, 8):
ADC Low Reference. Bypass to Pins
OF–/OF+ (Pins 55 to 56):
LVDS Over/Under Flow Output. 5, 6 with 0.1μF ceramic chip capacitor. Do not connect to High when an over or under fl ow has occurred. Pins 11, 12.
LVDS (Pin 57):
Output Mode Selection Pin. Connecting
REFHB (Pins 9, 10):
ADC High Reference. Bypass to LVDS to 0V selects full rate CMOS mode. Connecting LVDS Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not to 1/3VDD selects demux CMOS mode with simultaneous connect to Pins 5, 6. update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to V
REFLA (Pins 11, 12):
ADC Low Reference. Bypass to DD selects LVDS mode. Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5, 6 with a 2.2μF ceramic capacitor and to ground with 1μF
MODE (Pin 58):
Output Format and Clock Duty Cycle ceramic capacitor. Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle
VDD (Pins 13, 14, 15, 62, 63):
2.5V Supply. Bypass to stabilizer off. Connecting MODE to 1/3V GND with 0.1μF ceramic chip capacitors. DD selects offset binary output format and turns the clock duty cycle stabilizer
GND (Pins 16, 61, 64):
ADC Power Ground. on. Connecting MODE to 2/3VDD selects 2’s complement
ENC+ (Pin 17):
Encode Input. Conversion starts on the output format and turns the clock duty cycle stabilizer on. positive edge. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off.
ENC– (Pin 18):
Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1μF
SENSE (Pin 59):
Reference Programming Pin. Connecting ceramic for single-ended ENCODE signal. SENSE to VCM selects the internal reference and a ±0.5V input range. Connecting SENSE to V
SHDN (Pin 19):
Shutdown Mode Selection Pin. Connecting DD selects the internal reference and a ±1V input range. An external reference SHDN to GND and OE to GND results in normal operation greater than 0.5V and less than 1V applied to SENSE with the outputs enabled. Connecting SHDN to GND and OE selects an input range of ±V to V SENSE. ±1V is the largest valid DD results in normal operation with the outputs at input range. high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance.
VCM (Pin 60):
1.25V Output and Input Common Mode Bias. Connecting SHDN to V Bypass to ground with 2.2μF ceramic chip capacitor. DD and OE to VDD results in sleep mode with the outputs at high impedance.
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The
OE (Pin 20):
Output Enable Pin. Refer to SHDN pin func- exposed pad on the bottom of the package needs to be tion. soldered to ground.
D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54):
LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D11–/D11+ is the MSB. 224212fc 10 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS TIMING CHARACTERISTICS ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAMS APPLICATIONS INFORMATION PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS
PIN FUNCTIONS (LVDS Mode) OGND (Pins 25, 33, 41, 50):
Output Driver Ground.
AIN+ (Pins 1, 2):
Positive Differential Analog Input.
OVDD (Pins 26, 34, 42, 49):
Positive Supply for the Out-
AIN– (Pins 3, 4):
Negative Differential Analog Input. put Drivers. Bypass to ground with 0.1μF ceramic chip capacitor.
REFHA (Pins 5, 6):
ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11,
CLKOUT–/CLKOUT+ (Pins 35 to 36):
LVDS Data Valid 12 with a 2.2μF ceramic capacitor and to ground with 1μF Output. Latch data on rising edge of CLKOUT–, falling ceramic capacitor. edge of CLKOUT+.
REFLB (Pins 7, 8):
ADC Low Reference. Bypass to Pins
OF–/OF+ (Pins 55 to 56):
LVDS Over/Under Flow Output. 5, 6 with 0.1μF ceramic chip capacitor. Do not connect to High when an over or under fl ow has occurred. Pins 11, 12.
LVDS (Pin 57):
Output Mode Selection Pin. Connecting
REFHB (Pins 9, 10):
ADC High Reference. Bypass to LVDS to 0V selects full rate CMOS mode. Connecting LVDS Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not to 1/3VDD selects demux CMOS mode with simultaneous connect to Pins 5, 6. update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to V
REFLA (Pins 11, 12):
ADC Low Reference. Bypass to DD selects LVDS mode. Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5, 6 with a 2.2μF ceramic capacitor and to ground with 1μF
MODE (Pin 58):
Output Format and Clock Duty Cycle ceramic capacitor. Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle
VDD (Pins 13, 14, 15, 62, 63):
2.5V Supply. Bypass to stabilizer off. Connecting MODE to 1/3V GND with 0.1μF ceramic chip capacitors. DD selects offset binary output format and turns the clock duty cycle stabilizer
GND (Pins 16, 61, 64):
ADC Power Ground. on. Connecting MODE to 2/3VDD selects 2’s complement
ENC+ (Pin 17):
Encode Input. Conversion starts on the output format and turns the clock duty cycle stabilizer on. positive edge. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off.
ENC– (Pin 18):
Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1μF
SENSE (Pin 59):
Reference Programming Pin. Connecting ceramic for single-ended ENCODE signal. SENSE to VCM selects the internal reference and a ±0.5V input range. Connecting SENSE to V
SHDN (Pin 19):
Shutdown Mode Selection Pin. Connecting DD selects the internal reference and a ±1V input range. An external reference SHDN to GND and OE to GND results in normal operation greater than 0.5V and less than 1V applied to SENSE with the outputs enabled. Connecting SHDN to GND and OE selects an input range of ±V to V SENSE. ±1V is the largest valid DD results in normal operation with the outputs at input range. high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance.
VCM (Pin 60):
1.25V Output and Input Common Mode Bias. Connecting SHDN to V Bypass to ground with 2.2μF ceramic chip capacitor. DD and OE to VDD results in sleep mode with the outputs at high impedance.
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The
OE (Pin 20):
Output Enable Pin. Refer to SHDN pin func- exposed pad on the bottom of the package needs to be tion. soldered to ground.
D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54):
LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D11–/D11+ is the MSB. 224212fc 10 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS TIMING CHARACTERISTICS ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAMS APPLICATIONS INFORMATION PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS
