Datasheet LTC2262-14 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | 14-Bit, 150Msps Ultralow Power 1.8V ADC |
| Pages / Page | 28 / 1 — FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. LTC2262-14 … |
| File Format / Size | PDF / 680 Kb |
| Document Language | English |
FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. LTC2262-14 2-Tone FFT,. fIN = 68MHz and 69MHz
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LTC2262-14 14-Bit, 150Msps Ultralow Power 1.8V ADC
FEATURES DESCRIPTION
n 72.8dB SNR The LTC®2262-14 is a sampling 14-bit A/D converter n 88dB SFDR designed for digitizing high frequency, wide dynamic n Low Power: 149mW range signals. The LTC2262-14 is perfect for demanding n Single 1.8V Supply communications applications with AC performance that n CMOS, DDR CMOS or DDR LVDS Outputs includes 72.8dB SNR and 88dB spurious free dynamic n Selectable Input Ranges: 1VP-P to 2VP-P range (SFDR). Ultralow jitter of 0.17psRMS allows unders- n 800MHz Full-Power Bandwidth S/H ampling of IF frequencies with excel ent noise performance. n Optional Data Output Randomizer DC specs include ±1LSB INL (typical), ±0.3LSB DNL (typi- n Optional Clock Duty Cycle Stabilizer cal) and no missing codes over temperature. The transition n Shutdown and Nap Modes noise is a low 1.2LSBRMS. n Serial SPI Port for Configuration n Pin Compatible 14-Bit and 12-Bit Versions The digital outputs can be either full rate CMOS, double n 40-Pin (6mm × 6mm) QFN Package data rate CMOS, or double data rate LVDS. A separate output power supply al ows the CMOS output swing to
APPLICATIONS
range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differential y n Communications or single ended with a sine wave, PECL, LVDS, TTL or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Software Defined Radios lows high performance at full speed for a wide range of n Portable Medical Imaging clock duty cycles. n Multi-Channel Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Nondestructive Testing Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION LTC2262-14 2-Tone FFT, fIN = 68MHz and 69MHz
1.8V 1.2V 0 V TO 1.8V DD –10 OVDD –20 –30 + D13 14-BIT • –40 ANALOG CMOS INPUT CORRECTION OUTPUT PIPELINED • –50 INPUT OR S/H LOGIC DRIVERS ADC CORE – • LVDS –60 D0 –70 AMPLITUDE (dBFS) –80 OGND –90 CLOCK/DUTY –100 CYCLE –110 CONTROL –120 0 10 20 30 40 50 60 70 226214 TA01a GND FREQUENCY (MHz) 150MHz CLOCK 226214 TA01b 226214fc For more information www.linear.com/LTC2262-14 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
FEATURES DESCRIPTION
n 72.8dB SNR The LTC®2262-14 is a sampling 14-bit A/D converter n 88dB SFDR designed for digitizing high frequency, wide dynamic n Low Power: 149mW range signals. The LTC2262-14 is perfect for demanding n Single 1.8V Supply communications applications with AC performance that n CMOS, DDR CMOS or DDR LVDS Outputs includes 72.8dB SNR and 88dB spurious free dynamic n Selectable Input Ranges: 1VP-P to 2VP-P range (SFDR). Ultralow jitter of 0.17psRMS allows unders- n 800MHz Full-Power Bandwidth S/H ampling of IF frequencies with excel ent noise performance. n Optional Data Output Randomizer DC specs include ±1LSB INL (typical), ±0.3LSB DNL (typi- n Optional Clock Duty Cycle Stabilizer cal) and no missing codes over temperature. The transition n Shutdown and Nap Modes noise is a low 1.2LSBRMS. n Serial SPI Port for Configuration n Pin Compatible 14-Bit and 12-Bit Versions The digital outputs can be either full rate CMOS, double n 40-Pin (6mm × 6mm) QFN Package data rate CMOS, or double data rate LVDS. A separate output power supply al ows the CMOS output swing to
APPLICATIONS
range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differential y n Communications or single ended with a sine wave, PECL, LVDS, TTL or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Software Defined Radios lows high performance at full speed for a wide range of n Portable Medical Imaging clock duty cycles. n Multi-Channel Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Nondestructive Testing Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION LTC2262-14 2-Tone FFT, fIN = 68MHz and 69MHz
1.8V 1.2V 0 V TO 1.8V DD –10 OVDD –20 –30 + D13 14-BIT • –40 ANALOG CMOS INPUT CORRECTION OUTPUT PIPELINED • –50 INPUT OR S/H LOGIC DRIVERS ADC CORE – • LVDS –60 D0 –70 AMPLITUDE (dBFS) –80 OGND –90 CLOCK/DUTY –100 CYCLE –110 CONTROL –120 0 10 20 30 40 50 60 70 226214 TA01a GND FREQUENCY (MHz) 150MHz CLOCK 226214 TA01b 226214fc For more information www.linear.com/LTC2262-14 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
