Datasheet LTC2265-12, LTC2264-12, LTC2263-12 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 12-Bit, 65Msps Low Power Dual ADCs |
| Pages / Page | 34 / 6 — POWER REQUIREMENTS. The. denotes the specifications which apply over the … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
POWER REQUIREMENTS. The. denotes the specifications which apply over the full operating temperature
Model Line for this Datasheet
- LTC2263CUJ-12#PBF LTC2263CUJ-12#PBF LTC2263CUJ-12#TRPBF LTC2263CUJ-12#TRPBF LTC2263IUJ-12#PBF LTC2263IUJ-12#PBF LTC2263IUJ-12#TRPBF LTC2263IUJ-12#TRPBF
Text Version of Document
LTC2265-12/ LTC2264-12/LTC2263-12
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2265-12 LTC2264-12 LTC2263-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 82 98 52 63 42 50 mA IOVDD Digital Supply Current 1-Lane Mode, 1.75mA Mode 11 10 10 mA 1-Lane Mode, 3.5mA Mode 20 19 18 mA 2-Lane Mode, 1.75mA Mode l 15 18 15 18 14 17 mA 2-Lane Mode, 3.5mA Mode l 28 31 28 31 27 31 mA PDISS Power Dissipation 1-Lane Mode, 1.75mA Mode 167 112 94 mW 1-Lane Mode, 3.5mA Mode 184 128 108 mW 2-Lane Mode, 1.75mA Mode l 175 209 121 146 101 121 mW 2-Lane Mode, 3.5mA Mode l 198 232 144 169 124 146 mW PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 60 60 60 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 20 20 mW (No Increase for Sleep Mode)
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2265-12 LTC2264-12 LTC2263-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Notes 10, 11) l 5 65 5 40 5 25 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100 ns Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100 ns tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100 ns Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time 22654312fb 6 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2265-12 LTC2264-12 LTC2263-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 82 98 52 63 42 50 mA IOVDD Digital Supply Current 1-Lane Mode, 1.75mA Mode 11 10 10 mA 1-Lane Mode, 3.5mA Mode 20 19 18 mA 2-Lane Mode, 1.75mA Mode l 15 18 15 18 14 17 mA 2-Lane Mode, 3.5mA Mode l 28 31 28 31 27 31 mA PDISS Power Dissipation 1-Lane Mode, 1.75mA Mode 167 112 94 mW 1-Lane Mode, 3.5mA Mode 184 128 108 mW 2-Lane Mode, 1.75mA Mode l 175 209 121 146 101 121 mW 2-Lane Mode, 3.5mA Mode l 198 232 144 169 124 146 mW PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 60 60 60 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 20 20 mW (No Increase for Sleep Mode)
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2265-12 LTC2264-12 LTC2263-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Notes 10, 11) l 5 65 5 40 5 25 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100 ns Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100 ns tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100 ns Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time 22654312fb 6 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
