Datasheet LTC2265-14, LTC2264-14, LTC2263-14 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 14-Bit, 65Msps Low Power Dual ADCs |
| Pages / Page | 32 / 7 — TIMING DIAGRAMS. 2-Lane Output Mode, 16-Bit Serialization*. 2-Lane Output … |
| File Format / Size | PDF / 1.5 Mb |
| Document Language | English |
TIMING DIAGRAMS. 2-Lane Output Mode, 16-Bit Serialization*. 2-Lane Output Mode, 14-Bit Serialization
Model Line for this Datasheet
- LTC2263CUJ-14#PBF LTC2263CUJ-14#PBF LTC2263CUJ-14#TRPBF LTC2263CUJ-14#TRPBF LTC2263IUJ-14#PBF LTC2263IUJ-14#PBF LTC2263IUJ-14#TRPBF LTC2263IUJ-14#TRPBF
Text Version of Document
LTC2265-14/ LTC2264-14/LTC2263-14
TIMING DIAGRAMS 2-Lane Output Mode, 16-Bit Serialization*
tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ t t DATA tSER FRAME FR– FR+ tPD tSER OUT#A– D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 OUT#A+ OUT#B– D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 OUT#B+ 226514 TD01 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 *SEE THE DIGITAL OUTPUTS SECTION
2-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N + 2 N + 1 INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ t t DATA tSER FRAME FR– FR+ tPD tSER OUT#A– D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 OUT#A+ OUT#B– D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 OUT#B+ 226514 TD02 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 NOTE THAT IN THIS MODE, FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– 22654314fb 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
TIMING DIAGRAMS 2-Lane Output Mode, 16-Bit Serialization*
tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ t t DATA tSER FRAME FR– FR+ tPD tSER OUT#A– D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 OUT#A+ OUT#B– D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 OUT#B+ 226514 TD01 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 *SEE THE DIGITAL OUTPUTS SECTION
2-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N + 2 N + 1 INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ t t DATA tSER FRAME FR– FR+ tPD tSER OUT#A– D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 OUT#A+ OUT#B– D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 OUT#B+ 226514 TD02 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 NOTE THAT IN THIS MODE, FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– 22654314fb 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
