Datasheet LTC2298, LTC2297, LTC2296 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Dual 14-Bit, 65Msps Low Power 3V ADCs |
| Pages / Page | 28 / 1 — FEATURES. DESCRIPTIO. Integrated Dual 14-Bit ADCs. Sample Rate: … |
| File Format / Size | PDF / 804 Kb |
| Document Language | English |
FEATURES. DESCRIPTIO. Integrated Dual 14-Bit ADCs. Sample Rate: 65Msps/40Msps/25Msps. Single 3V Supply (2.7V to 3.4V)
Model Line for this Datasheet
- LTC2296CUP#PBF LTC2296CUP#PBF LTC2296CUP#TRPBF LTC2296CUP#TRPBF LTC2296IUP#PBF LTC2296IUP#PBF LTC2296IUP#TRPBF LTC2296IUP#TRPBF
Text Version of Document
LTC2298/LTC2297/LTC2296 Dual 14-Bit, 65/40/25Msps Low Power 3V ADCs
U FEATURES DESCRIPTIO
■
Integrated Dual 14-Bit ADCs
The LTC®2298/LTC2297/LTC2296 are 14-bit 65Msps/ ■
Sample Rate: 65Msps/40Msps/25Msps
40Msps/25Msps, low power dual 3V A/D converters de- ■
Single 3V Supply (2.7V to 3.4V)
signed for digitizing high frequency, wide dynamic range ■
Low Power: 400mW/235mW/150mW
signals. The LTC2298/LTC2297/LTC2296 are perfect for ■
74.3dB SNR
demanding imaging and communications applications ■
90dB SFDR
with AC performance that includes 74.3dB SNR and 90dB ■ 110dB Channel Isolation at 100MHz SFDR for signals at the Nyquist frequency. ■ Multiplexed or Separate Data Bus ■ Flexible Input: 1V DC specs include ±1.2LSB INL (typ), ±0.5LSB DNL (typ) P-P to 2VP-P Range ■ 575MHz Full Power Bandwidth S/H and no missing codes over temperature. The transition ■ Clock Duty Cycle Stabilizer noise is a low 1LSBRMS. ■ Shutdown and Nap Modes A single 3V supply allows low power operation. A separate ■ Pin Compatible Family output supply allows the outputs to drive 0.5V to 3.6V 105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit) logic. An optional multiplexer allows both channels to 80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit) share a digital output bus. 65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit) 40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit) A single-ended CLK input controls converter operation. An 25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit) optional clock duty cycle stabilizer allows high perfor- 10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit) mance at full speed for a wide range of clock duty cycles. ■ 64-Pin (9mm × 9mm) QFN Package , LTC and LT are registered trademarks of Linear Technology Corporation.
U
All other trademarks are the property of their respective owners.
APPLICATIO S
■ Wireless and Wired Broadband Communication ■ Imaging Systems ■ Spectral Analysis ■ Portable Instrumentation
U TYPICAL APPLICATIO LTC2298: SNR vs Input Frequency,
OV
–1dB, 2V Range, 65Msps
+ DD 14-BIT ANALOG INPUT 75 PIPELINED D13A INPUT A S/H OUTPUT • ADC CORE • – DRIVERS • D0A 74 OGND 73 CLK A CLOCK/DUTY CYCLE CONTROL MUX SNR (dBFS) 72 CLK B CLOCK/DUTY CYCLE CONTROL 71 OVDD D13B 70 + OUTPUT • 0 50 100 150 200 14-BIT • ANALOG • INPUT DRIVERS PIPELINED INPUT FREQUENCY (MHz) INPUT B D0B S/H ADC CORE 229876 TA01b – OGND 229876 TA01 229876fa 1
U FEATURES DESCRIPTIO
■
Integrated Dual 14-Bit ADCs
The LTC®2298/LTC2297/LTC2296 are 14-bit 65Msps/ ■
Sample Rate: 65Msps/40Msps/25Msps
40Msps/25Msps, low power dual 3V A/D converters de- ■
Single 3V Supply (2.7V to 3.4V)
signed for digitizing high frequency, wide dynamic range ■
Low Power: 400mW/235mW/150mW
signals. The LTC2298/LTC2297/LTC2296 are perfect for ■
74.3dB SNR
demanding imaging and communications applications ■
90dB SFDR
with AC performance that includes 74.3dB SNR and 90dB ■ 110dB Channel Isolation at 100MHz SFDR for signals at the Nyquist frequency. ■ Multiplexed or Separate Data Bus ■ Flexible Input: 1V DC specs include ±1.2LSB INL (typ), ±0.5LSB DNL (typ) P-P to 2VP-P Range ■ 575MHz Full Power Bandwidth S/H and no missing codes over temperature. The transition ■ Clock Duty Cycle Stabilizer noise is a low 1LSBRMS. ■ Shutdown and Nap Modes A single 3V supply allows low power operation. A separate ■ Pin Compatible Family output supply allows the outputs to drive 0.5V to 3.6V 105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit) logic. An optional multiplexer allows both channels to 80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit) share a digital output bus. 65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit) 40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit) A single-ended CLK input controls converter operation. An 25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit) optional clock duty cycle stabilizer allows high perfor- 10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit) mance at full speed for a wide range of clock duty cycles. ■ 64-Pin (9mm × 9mm) QFN Package , LTC and LT are registered trademarks of Linear Technology Corporation.
U
All other trademarks are the property of their respective owners.
APPLICATIO S
■ Wireless and Wired Broadband Communication ■ Imaging Systems ■ Spectral Analysis ■ Portable Instrumentation
U TYPICAL APPLICATIO LTC2298: SNR vs Input Frequency,
OV
–1dB, 2V Range, 65Msps
+ DD 14-BIT ANALOG INPUT 75 PIPELINED D13A INPUT A S/H OUTPUT • ADC CORE • – DRIVERS • D0A 74 OGND 73 CLK A CLOCK/DUTY CYCLE CONTROL MUX SNR (dBFS) 72 CLK B CLOCK/DUTY CYCLE CONTROL 71 OVDD D13B 70 + OUTPUT • 0 50 100 150 200 14-BIT • ANALOG • INPUT DRIVERS PIPELINED INPUT FREQUENCY (MHz) INPUT B D0B S/H ADC CORE 229876 TA01b – OGND 229876 TA01 229876fa 1
