Datasheet LTC2309 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 8-Channel, 12-Bit SAR ADC with I2C Interface |
| Pages / Page | 26 / 7 — (QFN). CH3-CH7 (Pins 1-5):. AD1 (Pin 15):. COM (Pin 6):. SCL (Pin 16):. … |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
(QFN). CH3-CH7 (Pins 1-5):. AD1 (Pin 15):. COM (Pin 6):. SCL (Pin 16):. REF (Pin 7):. SDA (Pin 17):. REFCOMP (Pin 8):
Model Line for this Datasheet
- LTC2309CF#PBF LTC2309CF#PBF LTC2309CF#TRPBF LTC2309CF#TRPBF LTC2309CUF#PBF LTC2309CUF#PBF LTC2309CUF#TRPBF LTC2309CUF#TRPBF LTC2309HF#PBF LTC2309HF#PBF LTC2309HF#TRPBF LTC2309HF#TRPBF LTC2309IF#PBF LTC2309IF#PBF LTC2309IF#TRPBF LTC2309IF#TRPBF LTC2309IUF#PBF LTC2309IUF#PBF LTC2309IUF#TRPBF LTC2309IUF#TRPBF
Text Version of Document
LTC2309 pIn FunCtIOns
(QFN) CH3-CH7 (Pins 1-5):
Channel 3 to Channel 7 Analog
AD1 (Pin 15):
Chip Address Control Pin. This pin is Inputs. CH3-CH7 can be configured as single-ended configured as a three-state (LOW, HIGH, floating) or differential input channels. See the Analog Input address control bit for the device I2C address. See Multiplexer section. Table 2 for address selection.
COM (Pin 6):
Common Input. This is the reference
SCL (Pin 16):
Serial Clock Pin of the I2C Interface. The point for all single-ended inputs. It must be free of LTC2309 can only act as a slave and the SCL pin only noise and should be connected to ground for unipolar accepts an external serial clock. Data is shifted into conversions and midway between GND and REFCOMP the SDA pin on the rising edges of the SCL clock and for bipolar conversions. output through the SDA pin on the falling edges of the
V
SCL clock.
REF (Pin 7):
2.5V Reference Output. Bypass to GND with a minimum 2.2µF ceramic capacitor. The internal
SDA (Pin 17):
Bidirectional Serial Data Line of the I2C reference may be overdriven by an external 2.5V refer- Interface. In transmitter mode (read), the conversion ence at this pin. result is output at the SDA pin, while in receiver mode
REFCOMP (Pin 8):
Reference Buffer Output. Bypass (write), the DIN word is input at the SDA pin to con- to GND with 10µF and 0.1µF ceramic capacitors in figure the ADC. The pin is high impedance during the parallel. Nominal output voltage is 4.096V. The internal data input mode and is an open-drain output (requires reference buffer driving this pin is disabled by ground- an appropriate pull-up device to VDD) during the data ing V output mode. REF , allowing REFCOMP to be overdriven by an external source.
CH0-CH2 (Pins 22-24):
Channel 0 to Channel 2 Analog
GND (Pins 9-11, 18-20):
Ground. All GND pins must Inputs. CH0-CH2 can be configured as single-ended be connected to a solid ground plane. or differential input channels. See the Analog Input Multiplexer section.
VDD (Pins 12, 13, 21):
5V Supply. The range of VDD is 4.75V to 5.25V. Bypass V
Exposed Pad (Pin 25):
Ground. Must be soldered DD to GND with a 10µF ceramic capacitor in paral el with three 0.1µF ceramic capacitors, directly to ground plane. one located as close as possible to each pin.
AD0 (Pin 14):
Chip Address Control Pin. This pin is configured as a three-state (LOW, HIGH, floating) ad- dress control bit for the device I2C address. See Table 2 for address selection. 2309fd Document Outline Features Description Applications Absolute Maximum Ratings Pin Configuration Order Information CONVERTER AND MULTIPLEXER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS I2C Inputs and Digital Outputs POWER REQUIREMENTS I2C TIMING CHARACTERISTICS ADC TIMING CHARACTERISTICS Typical Performance Characteristics Pin Functions Functional Block Diagram TIMING DIAGRAM Applications Information Package Description Revision History Typical Application Related Parts
(QFN) CH3-CH7 (Pins 1-5):
Channel 3 to Channel 7 Analog
AD1 (Pin 15):
Chip Address Control Pin. This pin is Inputs. CH3-CH7 can be configured as single-ended configured as a three-state (LOW, HIGH, floating) or differential input channels. See the Analog Input address control bit for the device I2C address. See Multiplexer section. Table 2 for address selection.
COM (Pin 6):
Common Input. This is the reference
SCL (Pin 16):
Serial Clock Pin of the I2C Interface. The point for all single-ended inputs. It must be free of LTC2309 can only act as a slave and the SCL pin only noise and should be connected to ground for unipolar accepts an external serial clock. Data is shifted into conversions and midway between GND and REFCOMP the SDA pin on the rising edges of the SCL clock and for bipolar conversions. output through the SDA pin on the falling edges of the
V
SCL clock.
REF (Pin 7):
2.5V Reference Output. Bypass to GND with a minimum 2.2µF ceramic capacitor. The internal
SDA (Pin 17):
Bidirectional Serial Data Line of the I2C reference may be overdriven by an external 2.5V refer- Interface. In transmitter mode (read), the conversion ence at this pin. result is output at the SDA pin, while in receiver mode
REFCOMP (Pin 8):
Reference Buffer Output. Bypass (write), the DIN word is input at the SDA pin to con- to GND with 10µF and 0.1µF ceramic capacitors in figure the ADC. The pin is high impedance during the parallel. Nominal output voltage is 4.096V. The internal data input mode and is an open-drain output (requires reference buffer driving this pin is disabled by ground- an appropriate pull-up device to VDD) during the data ing V output mode. REF , allowing REFCOMP to be overdriven by an external source.
CH0-CH2 (Pins 22-24):
Channel 0 to Channel 2 Analog
GND (Pins 9-11, 18-20):
Ground. All GND pins must Inputs. CH0-CH2 can be configured as single-ended be connected to a solid ground plane. or differential input channels. See the Analog Input Multiplexer section.
VDD (Pins 12, 13, 21):
5V Supply. The range of VDD is 4.75V to 5.25V. Bypass V
Exposed Pad (Pin 25):
Ground. Must be soldered DD to GND with a 10µF ceramic capacitor in paral el with three 0.1µF ceramic capacitors, directly to ground plane. one located as close as possible to each pin.
AD0 (Pin 14):
Chip Address Control Pin. This pin is configured as a three-state (LOW, HIGH, floating) ad- dress control bit for the device I2C address. See Table 2 for address selection. 2309fd Document Outline Features Description Applications Absolute Maximum Ratings Pin Configuration Order Information CONVERTER AND MULTIPLEXER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS I2C Inputs and Digital Outputs POWER REQUIREMENTS I2C TIMING CHARACTERISTICS ADC TIMING CHARACTERISTICS Typical Performance Characteristics Pin Functions Functional Block Diagram TIMING DIAGRAM Applications Information Package Description Revision History Typical Application Related Parts
