Datasheet LTC2309 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 8-Channel, 12-Bit SAR ADC with I2C Interface |
| Pages / Page | 26 / 8 — (TSSOP). REFCOMP (Pin 1):. SDA (Pin 7):. GND (Pins 2, 8 , 9):. CH0-CH7 … |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
(TSSOP). REFCOMP (Pin 1):. SDA (Pin 7):. GND (Pins 2, 8 , 9):. CH0-CH7 (Pins 11-18):. DD (Pins 3, 10):. AD0 (Pin 4):. COM (Pin 19):
Model Line for this Datasheet
- LTC2309CF#PBF LTC2309CF#PBF LTC2309CF#TRPBF LTC2309CF#TRPBF LTC2309CUF#PBF LTC2309CUF#PBF LTC2309CUF#TRPBF LTC2309CUF#TRPBF LTC2309HF#PBF LTC2309HF#PBF LTC2309HF#TRPBF LTC2309HF#TRPBF LTC2309IF#PBF LTC2309IF#PBF LTC2309IF#TRPBF LTC2309IF#TRPBF LTC2309IUF#PBF LTC2309IUF#PBF LTC2309IUF#TRPBF LTC2309IUF#TRPBF
Text Version of Document
LTC2309 pIn FunCtIOns
(TSSOP) REFCOMP (Pin 1):
Reference Buffer Output. Bypass
SDA (Pin 7):
Bidirectional Serial Data Line of the I2C to GND with 10µF and 0.1µF ceramic capacitors in Interface. In transmitter mode (read), the conversion parallel. Nominal output voltage is 4.096V. The internal result is output at the SDA pin, while in receiver mode reference buffer driving this pin is disabled by ground- (write), the DIN word is input at the SDA pin to con- ing VREF , allowing REFCOMP to be overdriven by an figure the ADC. The pin is high impedance during the external source. data input mode and is an open-drain output (requires
GND (Pins 2, 8 , 9):
Ground. All GND pins must be an appropriate pull-up device to VDD) during the data connected to a solid ground plane. output mode.
V CH0-CH7 (Pins 11-18):
Channel 0 to Channel 7 Analog
DD (Pins 3, 10):
5V Supply. The range of VDD is 4.75V to 5.25V. Bypass V Inputs. CH0-CH7 can be configured as single-ended DD to GND with a 10µF ceramic ca- pacitor in parallel with two 0.1µF ceramic capacitors, or differential input channels. See the Analog Input one located as close as possible to each pin. Multiplexer section.
AD0 (Pin 4):
Chip Address Control Pin. This pin is con-
COM (Pin 19):
Common Input. This is the reference figured as a three-state (LOW, HIGH, floating) address point for all single-ended inputs. It must be free of control bit for the device I2C address. See Table 2 for noise and should be connected to ground for unipolar address selection. conversions and midway between GND and REFCOMP for bipolar conversions.
AD1 (Pin 5):
Chip Address Control Pin. This pin is configured as a three-state (LOW, HIGH, floating)
VREF (Pin 20):
2.5V Reference Output. Bypass to GND address control bit for the device I2C address. See with a minimum 2.2µF ceramic capacitor. The internal Table 2 for address selection. reference may be overdriven by an external 2.5V refer- ence at this pin.
SCL (Pin 6):
Serial Clock Pin of the I2C Interface. The LTC2309 can only act as a slave and the SCL pin only accepts an external serial clock. Data is shifted into the SDA pin on the rising edges of the SCL clock and output through the SDA pin on the falling edges of the SCL clock. 2309fd Document Outline Features Description Applications Absolute Maximum Ratings Pin Configuration Order Information CONVERTER AND MULTIPLEXER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS I2C Inputs and Digital Outputs POWER REQUIREMENTS I2C TIMING CHARACTERISTICS ADC TIMING CHARACTERISTICS Typical Performance Characteristics Pin Functions Functional Block Diagram TIMING DIAGRAM Applications Information Package Description Revision History Typical Application Related Parts
(TSSOP) REFCOMP (Pin 1):
Reference Buffer Output. Bypass
SDA (Pin 7):
Bidirectional Serial Data Line of the I2C to GND with 10µF and 0.1µF ceramic capacitors in Interface. In transmitter mode (read), the conversion parallel. Nominal output voltage is 4.096V. The internal result is output at the SDA pin, while in receiver mode reference buffer driving this pin is disabled by ground- (write), the DIN word is input at the SDA pin to con- ing VREF , allowing REFCOMP to be overdriven by an figure the ADC. The pin is high impedance during the external source. data input mode and is an open-drain output (requires
GND (Pins 2, 8 , 9):
Ground. All GND pins must be an appropriate pull-up device to VDD) during the data connected to a solid ground plane. output mode.
V CH0-CH7 (Pins 11-18):
Channel 0 to Channel 7 Analog
DD (Pins 3, 10):
5V Supply. The range of VDD is 4.75V to 5.25V. Bypass V Inputs. CH0-CH7 can be configured as single-ended DD to GND with a 10µF ceramic ca- pacitor in parallel with two 0.1µF ceramic capacitors, or differential input channels. See the Analog Input one located as close as possible to each pin. Multiplexer section.
AD0 (Pin 4):
Chip Address Control Pin. This pin is con-
COM (Pin 19):
Common Input. This is the reference figured as a three-state (LOW, HIGH, floating) address point for all single-ended inputs. It must be free of control bit for the device I2C address. See Table 2 for noise and should be connected to ground for unipolar address selection. conversions and midway between GND and REFCOMP for bipolar conversions.
AD1 (Pin 5):
Chip Address Control Pin. This pin is configured as a three-state (LOW, HIGH, floating)
VREF (Pin 20):
2.5V Reference Output. Bypass to GND address control bit for the device I2C address. See with a minimum 2.2µF ceramic capacitor. The internal Table 2 for address selection. reference may be overdriven by an external 2.5V refer- ence at this pin.
SCL (Pin 6):
Serial Clock Pin of the I2C Interface. The LTC2309 can only act as a slave and the SCL pin only accepts an external serial clock. Data is shifted into the SDA pin on the rising edges of the SCL clock and output through the SDA pin on the falling edges of the SCL clock. 2309fd Document Outline Features Description Applications Absolute Maximum Ratings Pin Configuration Order Information CONVERTER AND MULTIPLEXER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS I2C Inputs and Digital Outputs POWER REQUIREMENTS I2C TIMING CHARACTERISTICS ADC TIMING CHARACTERISTICS Typical Performance Characteristics Pin Functions Functional Block Diagram TIMING DIAGRAM Applications Information Package Description Revision History Typical Application Related Parts
