Datasheet LTC2373-18 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 18-Bit, 1Msps, 8-Channel SAR ADC with 100dB SNR |
| Pages / Page | 50 / 7 — elecTrical characTerisTics. The. denotes the specifications which apply … |
| File Format / Size | PDF / 2.0 Mb |
| Document Language | English |
elecTrical characTerisTics. The. denotes the specifications which apply over the full operating
Model Line for this Datasheet
Text Version of Document
LTC2373-18
elecTrical characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
tSCK SCK Period (Notes 13, 14) l 10 ns tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK↑ (Note 13) l 4 ns tHSDISCK SDI Hold Time From SCK↑ (Note 13) l 1 ns tDSDO SDO Data Valid Delay from SCK↑ CL = 20pF, OVDD = 5.25V l 7.5 ns CL = 20pF, OVDD = 2.5V l 8 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDO SDO Data Remains Valid Delay from SCK↑ CL = 20pF (Note 6) l 1 ns tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 20pF (Note 6) l 5 ns tEN Bus Enable Time After RDL↓ (Note 13) l 16 ns tDIS Bus Relinquish Time After RDL↑ (Note 13) l 13 ns tWAKE REFBUF Wake-Up Time CREFBUF = 47μF, CREFIN = 0.1µF 200 ms tCNVMRST CNV↑ to MUX Starts Resetting Delay l 38 ns tMRST1 MUX Reset Time During Conversion l 36 ns tVLDMRST 8th SCK↑ to MUX Starts Resetting Delay After l 40 ns Programming 1st Valid Configuration Word tMRST2 MUX Reset Time During Acquisition After l 42 ns Programming 1st Valid Configuration Word
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings 0.5LSB when the output code flickers between 00 0000 0000 0000 0000 may cause permanent damage to the device. Exposure to any Absolute and 00 0000 0000 0000 0001. Bipolar zero-scale error is the offset volt- Maximum Rating condition for extended periods may affect device age measured from –0.5LSB when the output code flickers between 00 reliability and lifetime. 0000 0000 0000 0000 and 11 1111 1111 1111 1111. Fully differential full-
Note 2:
All voltage values are with respect to ground. scale error is the worst-case deviation of the first and last code transitions
Note 3:
When these pin voltages are taken below ground or above V from ideal and includes the effect of offset error. Unipolar full-scale error DD or OV is the deviation of the last code transition from the ideal and includes the DD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above V effect of offset error. Bipolar full-scale error is the worst-case deviation DD or OVDD without latchup. of the first and last code transitions from ideal and includes the effect of offset error.
Note 4:
VDD = 5V, OVDD = 2.5V, fSMPL = 1MHz, REFIN = 2.048V unless otherwise noted.
Note 9:
When REFBUF is overdriven, the internal reference buffer must be turned off by setting REFIN=0V.
Note 5:
Recommended operating conditions.
Note 10:
All specifications in dB are referred to a full-scale ±V
Note 6:
Guaranteed by design, not subject to test. REFBUF (fully differential), 0V to V
Note 7:
Integral nonlinearity is defined as the deviation of a code from a REFBUF (pseudo-differential unipolar), or ±VREFBUF/2 (pseudo-differential bipolar) input. straight line passing through the actual endpoints of the transfer curve.
Note 11:
Temperature coefficient is calculated by dividing the maximum The deviation is measured from the center of the quantization band. change in output voltage by the specified temperature range.
Note 8:
Fully differential zero-scale error is the offset voltage measured
Note 12:
f from –0.5LSB when the output code flickers between 01 1111 1111 1111 SMPL = 1MHz, IREFBUF varies proportionally with sample rate. 1111 and 10 0000 0000 0000 0000 in straight binary format and 00 0000
Note 13:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V 0000 0000 0000 and 11 1111 1111 1111 1111 in two’s complement and OVDD = 5.25V. format. Unipolar zero-scale error is the offset voltage measured from
Note 14:
tSCK of 10ns maximum allows a shift clock frequency up to 100MHz for rising edge capture. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 237318 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
237318f For more information www.linear.com/LTC2373-18 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram
elecTrical characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
tSCK SCK Period (Notes 13, 14) l 10 ns tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK↑ (Note 13) l 4 ns tHSDISCK SDI Hold Time From SCK↑ (Note 13) l 1 ns tDSDO SDO Data Valid Delay from SCK↑ CL = 20pF, OVDD = 5.25V l 7.5 ns CL = 20pF, OVDD = 2.5V l 8 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDO SDO Data Remains Valid Delay from SCK↑ CL = 20pF (Note 6) l 1 ns tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 20pF (Note 6) l 5 ns tEN Bus Enable Time After RDL↓ (Note 13) l 16 ns tDIS Bus Relinquish Time After RDL↑ (Note 13) l 13 ns tWAKE REFBUF Wake-Up Time CREFBUF = 47μF, CREFIN = 0.1µF 200 ms tCNVMRST CNV↑ to MUX Starts Resetting Delay l 38 ns tMRST1 MUX Reset Time During Conversion l 36 ns tVLDMRST 8th SCK↑ to MUX Starts Resetting Delay After l 40 ns Programming 1st Valid Configuration Word tMRST2 MUX Reset Time During Acquisition After l 42 ns Programming 1st Valid Configuration Word
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings 0.5LSB when the output code flickers between 00 0000 0000 0000 0000 may cause permanent damage to the device. Exposure to any Absolute and 00 0000 0000 0000 0001. Bipolar zero-scale error is the offset volt- Maximum Rating condition for extended periods may affect device age measured from –0.5LSB when the output code flickers between 00 reliability and lifetime. 0000 0000 0000 0000 and 11 1111 1111 1111 1111. Fully differential full-
Note 2:
All voltage values are with respect to ground. scale error is the worst-case deviation of the first and last code transitions
Note 3:
When these pin voltages are taken below ground or above V from ideal and includes the effect of offset error. Unipolar full-scale error DD or OV is the deviation of the last code transition from the ideal and includes the DD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above V effect of offset error. Bipolar full-scale error is the worst-case deviation DD or OVDD without latchup. of the first and last code transitions from ideal and includes the effect of offset error.
Note 4:
VDD = 5V, OVDD = 2.5V, fSMPL = 1MHz, REFIN = 2.048V unless otherwise noted.
Note 9:
When REFBUF is overdriven, the internal reference buffer must be turned off by setting REFIN=0V.
Note 5:
Recommended operating conditions.
Note 10:
All specifications in dB are referred to a full-scale ±V
Note 6:
Guaranteed by design, not subject to test. REFBUF (fully differential), 0V to V
Note 7:
Integral nonlinearity is defined as the deviation of a code from a REFBUF (pseudo-differential unipolar), or ±VREFBUF/2 (pseudo-differential bipolar) input. straight line passing through the actual endpoints of the transfer curve.
Note 11:
Temperature coefficient is calculated by dividing the maximum The deviation is measured from the center of the quantization band. change in output voltage by the specified temperature range.
Note 8:
Fully differential zero-scale error is the offset voltage measured
Note 12:
f from –0.5LSB when the output code flickers between 01 1111 1111 1111 SMPL = 1MHz, IREFBUF varies proportionally with sample rate. 1111 and 10 0000 0000 0000 0000 in straight binary format and 00 0000
Note 13:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V 0000 0000 0000 and 11 1111 1111 1111 1111 in two’s complement and OVDD = 5.25V. format. Unipolar zero-scale error is the offset voltage measured from
Note 14:
tSCK of 10ns maximum allows a shift clock frequency up to 100MHz for rising edge capture. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 237318 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
237318f For more information www.linear.com/LTC2373-18 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram
