Datasheet LTC2401, LTC2402 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 2-Channel 24-Bit µPower No Latency ∆ΣTM ADCs in MSOP-10 |
| Pages / Page | 32 / 8 — TYPICAL PERFOR A CE CHARACTERISTICS. INL vs Output Rate. Resolution vs … |
| File Format / Size | PDF / 368 Kb |
| Document Language | English |
TYPICAL PERFOR A CE CHARACTERISTICS. INL vs Output Rate. Resolution vs Output Rate. PIN FUNCTIONS. VCC (Pin 1):. FSSET (Pin 2):
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Text Version of Document
LTC2401/LTC2402
W U TYPICAL PERFOR A CE CHARACTERISTICS INL vs Output Rate Resolution vs Output Rate
24 24 VCC = 5V VREF = 5V FO = EXTERNAL 20 20 TA = –55°C TA = 90°C TA = 25°C 16 16 TA = –55°C INL (BITS) TA = 90°C RESOLUTION (BITS) 12 12 TA = 25°C VCC = 5V VREF = 5V FO = EXTERNAL 8 8 0 20 40 60 80 100 0 20 40 60 80 100 OUTPUT RATE (Hz) OUTPUT RATE (Hz) 24012 G28 24012 G29
U U U PIN FUNCTIONS VCC (Pin 1):
Positive Supply Voltage. Bypass to GND be connected directly to a ground plane through a mini- (Pin␣ 6) with a 10µF tantalum capacitor in parallel with mum length trace or it should be the single-point-ground 0.1µF ceramic capacitor as close to the part as possible. in a single-point grounding system.
FSSET (Pin 2):
Full-Scale Set Input. This pin defines the
CS (Pin 7):
Active LOW Digital Input. A LOW on this pin full-scale input value. When VIN = FSSET, the ADC outputs enables the SDO digital output and wakes up the ADC. full scale (FFFFFH). The total reference voltage is Following each conversion, the ADC automatically enters FSSET – ZSSET. the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW on CS wakes up the ADC. A
CH0, CH1 (Pins 4, 3):
Analog Input Channels. The input LOW-to-HIGH transition on this pin disables the SDO voltage range is – 0.125 • VREF to 1.125 • VREF. For digital output. A LOW-to-HIGH transition on CS during the VREF > 2.5V, the input voltage range may be limited by the Data Output transfer aborts the data transfer and starts a absolute maximum rating of – 0.3V to VCC + 0.3V. Conver- new conversion. sions are performed alternately between CH0 and CH1 for the LTC2402. Pin 4 is a No Connect (NC) on
SDO (Pin 8):
Three-State Digital Output. During the data the LTC2401. output period, this pin is used for serial data output. When the chip select CS is HIGH (CS = V
ZS
CC), the SDO pin is in a
SET (Pin 5):
Zero-Scale Set Input. This pin defines the high impedance state. During the Conversion and Sleep zero-scale input value. When VIN = ZSSET, the ADC periods, this pin can be used as a conversion status out- outputs zero scale (00000H). put. The conversion status can be observed by pulling CS
GND (Pin 6):
Ground. Shared pin for analog ground, LOW. digital ground, reference ground and signal ground. Should 8
W U TYPICAL PERFOR A CE CHARACTERISTICS INL vs Output Rate Resolution vs Output Rate
24 24 VCC = 5V VREF = 5V FO = EXTERNAL 20 20 TA = –55°C TA = 90°C TA = 25°C 16 16 TA = –55°C INL (BITS) TA = 90°C RESOLUTION (BITS) 12 12 TA = 25°C VCC = 5V VREF = 5V FO = EXTERNAL 8 8 0 20 40 60 80 100 0 20 40 60 80 100 OUTPUT RATE (Hz) OUTPUT RATE (Hz) 24012 G28 24012 G29
U U U PIN FUNCTIONS VCC (Pin 1):
Positive Supply Voltage. Bypass to GND be connected directly to a ground plane through a mini- (Pin␣ 6) with a 10µF tantalum capacitor in parallel with mum length trace or it should be the single-point-ground 0.1µF ceramic capacitor as close to the part as possible. in a single-point grounding system.
FSSET (Pin 2):
Full-Scale Set Input. This pin defines the
CS (Pin 7):
Active LOW Digital Input. A LOW on this pin full-scale input value. When VIN = FSSET, the ADC outputs enables the SDO digital output and wakes up the ADC. full scale (FFFFFH). The total reference voltage is Following each conversion, the ADC automatically enters FSSET – ZSSET. the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW on CS wakes up the ADC. A
CH0, CH1 (Pins 4, 3):
Analog Input Channels. The input LOW-to-HIGH transition on this pin disables the SDO voltage range is – 0.125 • VREF to 1.125 • VREF. For digital output. A LOW-to-HIGH transition on CS during the VREF > 2.5V, the input voltage range may be limited by the Data Output transfer aborts the data transfer and starts a absolute maximum rating of – 0.3V to VCC + 0.3V. Conver- new conversion. sions are performed alternately between CH0 and CH1 for the LTC2402. Pin 4 is a No Connect (NC) on
SDO (Pin 8):
Three-State Digital Output. During the data the LTC2401. output period, this pin is used for serial data output. When the chip select CS is HIGH (CS = V
ZS
CC), the SDO pin is in a
SET (Pin 5):
Zero-Scale Set Input. This pin defines the high impedance state. During the Conversion and Sleep zero-scale input value. When VIN = ZSSET, the ADC periods, this pin can be used as a conversion status out- outputs zero scale (00000H). put. The conversion status can be observed by pulling CS
GND (Pin 6):
Ground. Shared pin for analog ground, LOW. digital ground, reference ground and signal ground. Should 8
