Datasheet LTC2414, LTC2418 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 8-/16-Channel 24-Bit No Latency ∆ΣTM ADCs |
| Pages / Page | 50 / 10 — pin FuncTions CH0 to CH15 (Pin 21 to Pin 28 and Pin 1 to Pin 8):. VCC … |
| File Format / Size | PDF / 892 Kb |
| Document Language | English |
pin FuncTions CH0 to CH15 (Pin 21 to Pin 28 and Pin 1 to Pin 8):. VCC (Pin 9):. SCK (Pin 18):. COM (Pin 10):. FO (Pin 19):
Model Line for this Datasheet
Text Version of Document
LTC2414/LTC2418
pin FuncTions CH0 to CH15 (Pin 21 to Pin 28 and Pin 1 to Pin 8):
Analog is in a high impedance state. During the Conversion and Inputs. May be programmed for single-ended or differ- Sleep periods, this pin is used as the conversion status ential mode. CH8 to CH15 (Pin 1 to Pin 8) not connected output. The conversion status can be observed by pulling on the LTC2414. CS LOW.
VCC (Pin 9):
Positive Supply Voltage. Bypass to GND
SCK (Pin 18):
Bidirectional Digital Clock Pin. In Internal (Pin 15) with a 10µF tantalum capacitor in parallel with Serial Clock Operation mode, SCK is used as the digital 0.1µF ceramic capacitor as close to the part as possible. output for the internal serial interface clock during the
COM (Pin 10):
The common negative input (IN–) for all Data Output period. In External Serial Clock Operation single-ended multiplexer configurations. The voltage on mode, SCK is used as the digital input for the external se- Channel 0 to 15 and COM input pins can have any value rial interface clock during the Data Output period. A weak between GND – 0.3V and V internal pull-up is automatically activated in Internal Serial CC + 0.3V. Within these limits, the two selected inputs (IN+ and IN–) provide a bipolar in- Clock Operation mode. The Serial Clock Operation mode put range (V is determined by the logic level applied to the SCK pin at IN = IN+ – IN–) from – 0.5 • VREF to 0.5 • VREF. Outside this input range, the converter produces unique power up or during the most recent falling edge of CS. overrange and underrange output codes.
FO (Pin 19):
Frequency Control Pin. Digital input that
REF+ (Pin 11), REF– (Pin 12):
Differential Reference Input. controls the ADC’s notch frequencies and conversion The voltage on these pins can have any value between time. When the FO pin is connected to VCC (FO = VCC), the GND and V converter uses its internal oscillator and the digital filter CC as long as the positive reference input, REF+, is maintained more positive than the negative reference first null is located at 50Hz. When the FO pin is connected input, REF –, by at least 0.1V. to GND (FO = 0V), the converter uses its internal oscillator and the digital filter first null is located at 60Hz. When FO is
GND (Pin 15):
Ground. Connect this pin to a ground plane driven by an external clock signal with a frequency fEOSC, through a low impedance connection. the converters use this signal as their system clock and the
CS (Pin 16):
Active LOW Digital Input. A LOW on this pin digital filter first null is located at a frequency fEOSC/2560. enables the SDO digital output and wakes up the ADC.
SDI (Pin 20):
Serial Digital Data Input. During the Data Following each conversion the ADC automatically enters Output period, this pin is used to shift in the multiplexer the Sleep mode and remains in this low power state as address started from the first rising SCK edge. During the long as CS is HIGH. A LOW-to-HIGH transition on CS Conversion and Sleep periods, this pin is in the DON’T during the Data Output transfer aborts the data transfer CARE state. However, a HIGH or LOW logic level should and starts a new conversion. be maintained on SDI in the DON’T CARE mode to avoid
SDO (Pin 17):
Three-State Digital Output. During the Data an excessive current in the SDI input buffers. Output period, this pin is used as the serial data output.
NC Pins:
Do Not Connect. When the chip select CS is HIGH (CS = VCC), the SDO pin 241418fb 10 For more information www.linear.com/LTC2414
pin FuncTions CH0 to CH15 (Pin 21 to Pin 28 and Pin 1 to Pin 8):
Analog is in a high impedance state. During the Conversion and Inputs. May be programmed for single-ended or differ- Sleep periods, this pin is used as the conversion status ential mode. CH8 to CH15 (Pin 1 to Pin 8) not connected output. The conversion status can be observed by pulling on the LTC2414. CS LOW.
VCC (Pin 9):
Positive Supply Voltage. Bypass to GND
SCK (Pin 18):
Bidirectional Digital Clock Pin. In Internal (Pin 15) with a 10µF tantalum capacitor in parallel with Serial Clock Operation mode, SCK is used as the digital 0.1µF ceramic capacitor as close to the part as possible. output for the internal serial interface clock during the
COM (Pin 10):
The common negative input (IN–) for all Data Output period. In External Serial Clock Operation single-ended multiplexer configurations. The voltage on mode, SCK is used as the digital input for the external se- Channel 0 to 15 and COM input pins can have any value rial interface clock during the Data Output period. A weak between GND – 0.3V and V internal pull-up is automatically activated in Internal Serial CC + 0.3V. Within these limits, the two selected inputs (IN+ and IN–) provide a bipolar in- Clock Operation mode. The Serial Clock Operation mode put range (V is determined by the logic level applied to the SCK pin at IN = IN+ – IN–) from – 0.5 • VREF to 0.5 • VREF. Outside this input range, the converter produces unique power up or during the most recent falling edge of CS. overrange and underrange output codes.
FO (Pin 19):
Frequency Control Pin. Digital input that
REF+ (Pin 11), REF– (Pin 12):
Differential Reference Input. controls the ADC’s notch frequencies and conversion The voltage on these pins can have any value between time. When the FO pin is connected to VCC (FO = VCC), the GND and V converter uses its internal oscillator and the digital filter CC as long as the positive reference input, REF+, is maintained more positive than the negative reference first null is located at 50Hz. When the FO pin is connected input, REF –, by at least 0.1V. to GND (FO = 0V), the converter uses its internal oscillator and the digital filter first null is located at 60Hz. When FO is
GND (Pin 15):
Ground. Connect this pin to a ground plane driven by an external clock signal with a frequency fEOSC, through a low impedance connection. the converters use this signal as their system clock and the
CS (Pin 16):
Active LOW Digital Input. A LOW on this pin digital filter first null is located at a frequency fEOSC/2560. enables the SDO digital output and wakes up the ADC.
SDI (Pin 20):
Serial Digital Data Input. During the Data Following each conversion the ADC automatically enters Output period, this pin is used to shift in the multiplexer the Sleep mode and remains in this low power state as address started from the first rising SCK edge. During the long as CS is HIGH. A LOW-to-HIGH transition on CS Conversion and Sleep periods, this pin is in the DON’T during the Data Output transfer aborts the data transfer CARE state. However, a HIGH or LOW logic level should and starts a new conversion. be maintained on SDI in the DON’T CARE mode to avoid
SDO (Pin 17):
Three-State Digital Output. During the Data an excessive current in the SDI input buffers. Output period, this pin is used as the serial data output.
NC Pins:
Do Not Connect. When the chip select CS is HIGH (CS = VCC), the SDO pin 241418fb 10 For more information www.linear.com/LTC2414
