Datasheet LTC2430, LTC2431 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 20-Bit No Latency ∆Σ™ ADCs with Differential Input and Differential Reference |
| Pages / Page | 40 / 10 — PI FU CTIO S (LTC2431). SDO (Pin 8):. O (Pin 10):. SCK (Pin 9):. FU CTIO … |
| File Format / Size | PDF / 466 Kb |
| Document Language | English |
PI FU CTIO S (LTC2431). SDO (Pin 8):. O (Pin 10):. SCK (Pin 9):. FU CTIO AL BLOCK DIAGRA. Figure 1. TEST CIRCUITS
Model Line for this Datasheet
Text Version of Document
LTC2430/LTC2431
U U U PI FU CTIO S (LTC2431) SDO (Pin 8):
Three-State Digital Output. During the Data Clock Operation mode. The Serial Clock Operation mode is Output period, this pin is used as the serial data output. determined by the logic level applied to the SCK pin at When the chip select CS is HIGH (CS = VCC), the SDO pin power up or during the most recent falling edge of CS. is in a high impedance state. During the Conversion and
F
Sleep periods, this pin is used as the conversion status
O (Pin 10):
Frequency Control Pin. Digital input that controls the ADC’s notch frequencies and conversion output. The conversion status can be observed by pulling time. When the F CS LOW. O pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter
SCK (Pin 9):
Bidirectional Digital Clock Pin. In Internal first null is located at 50Hz. When the FO pin is connected Serial Clock Operation mode, SCK is used as the digital to GND (FO = OV), the converter uses its internal oscillator output for the internal serial interface clock during the Data and the digital filter first null is located at 60Hz. When FO Output period. In External Serial Clock Operation mode, is driven by an external clock signal with a frequency fEOSC, SCK is used as the digital input for the external serial the converter uses this signal as its system clock and the interface clock during the Data Output period. A weak digital filter first null is located at a frequency fEOSC/2560. internal pull-up is automatically activated in Internal Serial
U U W FU CTIO AL BLOCK DIAGRA
INTERNAL VCC OSCILLATOR GND AUTOCALIBRATION F AND CONTROL O (INT/EXT) IN+ + IN– – ∫ ∫ ∫ SDO SERIAL ∑ ADC SCK INTERFACE REF+ CS REF – DECIMATING FIR DAC 2431 FD
Figure 1 TEST CIRCUITS
VCC 1.69k SDO SDO 1.69k CLOAD = 20pF CLOAD = 20pF 2431 TA03 2431 TA04 Hi-Z TO VOH Hi-Z TO VOL VOL TO VOH VOH TO VOL VOH TO Hi-Z VOL TO Hi-Z 24301f 10
U U U PI FU CTIO S (LTC2431) SDO (Pin 8):
Three-State Digital Output. During the Data Clock Operation mode. The Serial Clock Operation mode is Output period, this pin is used as the serial data output. determined by the logic level applied to the SCK pin at When the chip select CS is HIGH (CS = VCC), the SDO pin power up or during the most recent falling edge of CS. is in a high impedance state. During the Conversion and
F
Sleep periods, this pin is used as the conversion status
O (Pin 10):
Frequency Control Pin. Digital input that controls the ADC’s notch frequencies and conversion output. The conversion status can be observed by pulling time. When the F CS LOW. O pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter
SCK (Pin 9):
Bidirectional Digital Clock Pin. In Internal first null is located at 50Hz. When the FO pin is connected Serial Clock Operation mode, SCK is used as the digital to GND (FO = OV), the converter uses its internal oscillator output for the internal serial interface clock during the Data and the digital filter first null is located at 60Hz. When FO Output period. In External Serial Clock Operation mode, is driven by an external clock signal with a frequency fEOSC, SCK is used as the digital input for the external serial the converter uses this signal as its system clock and the interface clock during the Data Output period. A weak digital filter first null is located at a frequency fEOSC/2560. internal pull-up is automatically activated in Internal Serial
U U W FU CTIO AL BLOCK DIAGRA
INTERNAL VCC OSCILLATOR GND AUTOCALIBRATION F AND CONTROL O (INT/EXT) IN+ + IN– – ∫ ∫ ∫ SDO SERIAL ∑ ADC SCK INTERFACE REF+ CS REF – DECIMATING FIR DAC 2431 FD
Figure 1 TEST CIRCUITS
VCC 1.69k SDO SDO 1.69k CLOAD = 20pF CLOAD = 20pF 2431 TA03 2431 TA04 Hi-Z TO VOH Hi-Z TO VOL VOL TO VOH VOH TO VOL VOH TO Hi-Z VOL TO Hi-Z 24301f 10
