Datasheet LTC2446, LTC2447 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 24-Bit High Speed 8-Channel ∆Σ ADCs with Selectable Multiple Reference Inputs |
| Pages / Page | 30 / 6 — PIN FUNCTIONS COM (Pin 7):. SDI (Pin 34):. CH0 to CH7 (Pins 8, 9, 12, 13, … |
| File Format / Size | PDF / 619 Kb |
| Document Language | English |
PIN FUNCTIONS COM (Pin 7):. SDI (Pin 34):. CH0 to CH7 (Pins 8, 9, 12, 13, 16, 17, 20, 21):. FO (Pin 35):
Model Line for this Datasheet
Text Version of Document
LTC2446/LTC2447
PIN FUNCTIONS COM (Pin 7):
The common negative input (IN–) for all
SDI (Pin 34):
Serial Data Input. This pin is used to select single-ended multiplexer configurations. The voltage the speed, 1× or 2× mode, resolution, input channel and on CH0-CH7 and COM pins can have any value between reference input for the next conversion cycle. At initial GND – 0.3V to VCC + 0.3V. Within these limits, the two power-up, the default mode of operation is CH0-CH1, selected inputs (IN+ and IN–) provide a bipolar input range VREF01, OSR of 256, and 1× mode. The serial data input (VIN = IN+ – IN–) from –0.5 • VREF to 0.5 • VREF. Outside contains an enable bit which determines if a new channel/ this input range, the converter produces unique over-range speed is selected. If this bit is low the following conver- and under-range output codes. sion remains at the same speed and selected channel. The
CH0 to CH7 (Pins 8, 9, 12, 13, 16, 17, 20, 21):
Analog serial data input is applied to the device under control of Inputs. May be programmed for Single-ended or Differ- the serial clock (SCK) during the data output cycle. The ential mode. first conversion following a new channel/speed is valid.
V + – + FO (Pin 35):
Frequency Control Pin. Digital input that con-
REF01 (Pin 11), VREF01 (Pin 10) VREF23 (Pin 15), V – + –
trols the internal conversion clock. When FO is connected
REF23 (Pin 14), VREF45 (Pin 19), VREF45 (Pin 18), V + –
to VCC or GND, the converter uses its internal oscillator.
REF67 (Pin 23), VREF67 (Pin 22):
Differential Refer- ence Inputs. The voltage on these pins can be anywhere
CS (Pin 36):
Active Low Chip Select. A LOW on this pin between 0V and VCC as long as the positive reference enables the SDO digital output and wakes up the ADC. input (V + + + + EF01 , VREF23 , VREF45 , VREF67 ) is greater than Following each conversion the ADC automatically enters the corresponding negative reference input (V – REF01 , the sleep mode and remains in this low power state as V – – – REF23 , VREF45 , VREF67 ) by at least 100mV. long as CS is HIGH. A LOW-to-HIGH transition on CS dur-
NC (Pins 24, 25, 26, 27):
LTC2446 No Connect. These ing the Data Output aborts the data transfer and starts a pins can either be tied to ground or left floating. new conversion.
MUXOUTP (Pin 24):
LTC2447 Positive Input Channel
SDO (Pin 37):
Three-State Digital Output. During the data Multiplexer Output. Used to drive the input to an external output period, this pin is used as serial data output. When buffer/amplifier for the selected positive input signal (IN+). the chip select CS is HIGH (CS = VCC) the SDO pin is in a high impedance state. During the conversion and sleep
ADCINP (Pin 25):
LTC2447 Positive ADC Input. Tie to periods, this pin is used as the conversion status output. output of buffer/amplifier driven by MUXOUTP. The conversion status can be observed by pulling CS LOW.
ADCINN (Pin 26):
LTC2447 Negative ADC Input. Tie to This signal is HIGH while the conversion is in progress output of buffer/amplifier driven by MUXOUTN. and goes LOW once the conversion is complete.
MUXOUTN (Pin 27):
LTC2447 Negative Input Chan-
SCK (Pin 38):
Bidirectional Digital Clock Pin. In internal nel Multiplexer Output. Used to drive the input to an serial clock operation mode, SCK is used as a digital external buffer/amplifier for the selected negative input output for the internal serial interface clock during the signal (IN–). data output period. In the external serial clock operation mode, SCK is used as the digital input for the external
VCC (Pin 28):
Positive Supply Voltage. Bypass to GND with serial interface clock during the data output period. The a 10µF tantalum capacitor in parallel with a 0.1µF ceramic serial clock operation mode is determined by the logic capacitor as close to the part as possible. level applied to the EXT pin.
V + – REFG (Pin 29), VREFG (Pin 30):
Global Reference In-
Exposed Pad (Pin 39):
Ground. The exposed pad on the put. This differential reference input can be used for any bottom of the package must be soldered to the PCB ground. input channel selected through a single bit in the digital For Prototyping purposes, this pin may remain floating. input word. 24467fb 6 For more information www.linear.com/LTC2446 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Test Circuit Timing Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS COM (Pin 7):
The common negative input (IN–) for all
SDI (Pin 34):
Serial Data Input. This pin is used to select single-ended multiplexer configurations. The voltage the speed, 1× or 2× mode, resolution, input channel and on CH0-CH7 and COM pins can have any value between reference input for the next conversion cycle. At initial GND – 0.3V to VCC + 0.3V. Within these limits, the two power-up, the default mode of operation is CH0-CH1, selected inputs (IN+ and IN–) provide a bipolar input range VREF01, OSR of 256, and 1× mode. The serial data input (VIN = IN+ – IN–) from –0.5 • VREF to 0.5 • VREF. Outside contains an enable bit which determines if a new channel/ this input range, the converter produces unique over-range speed is selected. If this bit is low the following conver- and under-range output codes. sion remains at the same speed and selected channel. The
CH0 to CH7 (Pins 8, 9, 12, 13, 16, 17, 20, 21):
Analog serial data input is applied to the device under control of Inputs. May be programmed for Single-ended or Differ- the serial clock (SCK) during the data output cycle. The ential mode. first conversion following a new channel/speed is valid.
V + – + FO (Pin 35):
Frequency Control Pin. Digital input that con-
REF01 (Pin 11), VREF01 (Pin 10) VREF23 (Pin 15), V – + –
trols the internal conversion clock. When FO is connected
REF23 (Pin 14), VREF45 (Pin 19), VREF45 (Pin 18), V + –
to VCC or GND, the converter uses its internal oscillator.
REF67 (Pin 23), VREF67 (Pin 22):
Differential Refer- ence Inputs. The voltage on these pins can be anywhere
CS (Pin 36):
Active Low Chip Select. A LOW on this pin between 0V and VCC as long as the positive reference enables the SDO digital output and wakes up the ADC. input (V + + + + EF01 , VREF23 , VREF45 , VREF67 ) is greater than Following each conversion the ADC automatically enters the corresponding negative reference input (V – REF01 , the sleep mode and remains in this low power state as V – – – REF23 , VREF45 , VREF67 ) by at least 100mV. long as CS is HIGH. A LOW-to-HIGH transition on CS dur-
NC (Pins 24, 25, 26, 27):
LTC2446 No Connect. These ing the Data Output aborts the data transfer and starts a pins can either be tied to ground or left floating. new conversion.
MUXOUTP (Pin 24):
LTC2447 Positive Input Channel
SDO (Pin 37):
Three-State Digital Output. During the data Multiplexer Output. Used to drive the input to an external output period, this pin is used as serial data output. When buffer/amplifier for the selected positive input signal (IN+). the chip select CS is HIGH (CS = VCC) the SDO pin is in a high impedance state. During the conversion and sleep
ADCINP (Pin 25):
LTC2447 Positive ADC Input. Tie to periods, this pin is used as the conversion status output. output of buffer/amplifier driven by MUXOUTP. The conversion status can be observed by pulling CS LOW.
ADCINN (Pin 26):
LTC2447 Negative ADC Input. Tie to This signal is HIGH while the conversion is in progress output of buffer/amplifier driven by MUXOUTN. and goes LOW once the conversion is complete.
MUXOUTN (Pin 27):
LTC2447 Negative Input Chan-
SCK (Pin 38):
Bidirectional Digital Clock Pin. In internal nel Multiplexer Output. Used to drive the input to an serial clock operation mode, SCK is used as a digital external buffer/amplifier for the selected negative input output for the internal serial interface clock during the signal (IN–). data output period. In the external serial clock operation mode, SCK is used as the digital input for the external
VCC (Pin 28):
Positive Supply Voltage. Bypass to GND with serial interface clock during the data output period. The a 10µF tantalum capacitor in parallel with a 0.1µF ceramic serial clock operation mode is determined by the logic capacitor as close to the part as possible. level applied to the EXT pin.
V + – REFG (Pin 29), VREFG (Pin 30):
Global Reference In-
Exposed Pad (Pin 39):
Ground. The exposed pad on the put. This differential reference input can be used for any bottom of the package must be soldered to the PCB ground. input channel selected through a single bit in the digital For Prototyping purposes, this pin may remain floating. input word. 24467fb 6 For more information www.linear.com/LTC2446 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Test Circuit Timing Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
