Datasheet LTC2450 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Easy-to-Use, Ultra-Tiny 16-Bit ΔΣ ADC |
| Pages / Page | 20 / 9 — APPLICATIONS INFORMATION. Serial Interface Operation Modes. Conversion … |
| File Format / Size | PDF / 207 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Serial Interface Operation Modes. Conversion Status Monitor. SERIAL INTERFACE
Model Line for this Datasheet
Text Version of Document
LTC2450
APPLICATIONS INFORMATION
During the data output operation the CS input pin must CONVERT and SLEEP states to assess the conversion be pulled low (CS = LOW). The data output process starts status and during the DATA OUTPUT state to read the with the most signifi cant bit of the result being present conversion result, and to trigger a new conversion. at the SDO output pin (SDO = D15) once CS goes low. A new data bit appears at the SDO output pin following every
Serial Interface Operation Modes
falling edge detected at the SCK input pin. The output data The following are a few of the more common interface can be latched by the user using the rising edge of SCK. operation examples. Many more valid control and serial data output operation sequences can be constructed based
Conversion Status Monitor
upon the above description of the function of the three For certain applications, the user may wish to monitor digital interface pins. the LTC2450 conversion status. This can be achieved The modes of operation can be summarized as follows: by holding SCK HIGH during the conversion cycle. In this condition, whenever the CS input pin is pulled low 1) The LTC2450 functions with SCK idle high (commonly (CS = LOW), the SDO output pin will provide an indication known as CPOL = 1) or idle low (commonly known as of the conversion status. SDO = HIGH is an indication of CPOL = 0). a conversion cycle in progress while SDO = LOW is an 2) After the 16th bit is read, the user can choose one of indication of a completed conversion cycle. An example two ways to begin a new conversion. First, one can of such a sequence is shown in Figure 4. pull CS high (CS = ↑). Second, one can use a high-low Conversion status monitoring, while possible, is not re- transition on SCK (SCK = ↓). quired for LTC2450 as its conversion time is fi xed and equal 3) In a similar vein, at any time during the Data Output at approximately 33.3ms (42ms maximum). Therefore, state, pulling CS high (CS = ↑) causes the part to leave external timing can be used to determine the completion of a the I/O state, abort the output and begin a new conver- conversion cycle. sion. 4) When SCK = HIGH, it is possible to monitor the conver-
SERIAL INTERFACE
sion status by pulling CS low and watching for SDO to The LTC2450 transmits the conversion result and receives go low. This feature is available only in the idle-high the start of conversion command through a synchronous (CPOL = 1) mode. 3-wire interface. This interface can be used during the t1 t2 CS SDO SCK = HI CONVERT SLEEP 2450 F03
Figure 4. Conversion Status Monitoring Mode
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APPLICATIONS INFORMATION
During the data output operation the CS input pin must CONVERT and SLEEP states to assess the conversion be pulled low (CS = LOW). The data output process starts status and during the DATA OUTPUT state to read the with the most signifi cant bit of the result being present conversion result, and to trigger a new conversion. at the SDO output pin (SDO = D15) once CS goes low. A new data bit appears at the SDO output pin following every
Serial Interface Operation Modes
falling edge detected at the SCK input pin. The output data The following are a few of the more common interface can be latched by the user using the rising edge of SCK. operation examples. Many more valid control and serial data output operation sequences can be constructed based
Conversion Status Monitor
upon the above description of the function of the three For certain applications, the user may wish to monitor digital interface pins. the LTC2450 conversion status. This can be achieved The modes of operation can be summarized as follows: by holding SCK HIGH during the conversion cycle. In this condition, whenever the CS input pin is pulled low 1) The LTC2450 functions with SCK idle high (commonly (CS = LOW), the SDO output pin will provide an indication known as CPOL = 1) or idle low (commonly known as of the conversion status. SDO = HIGH is an indication of CPOL = 0). a conversion cycle in progress while SDO = LOW is an 2) After the 16th bit is read, the user can choose one of indication of a completed conversion cycle. An example two ways to begin a new conversion. First, one can of such a sequence is shown in Figure 4. pull CS high (CS = ↑). Second, one can use a high-low Conversion status monitoring, while possible, is not re- transition on SCK (SCK = ↓). quired for LTC2450 as its conversion time is fi xed and equal 3) In a similar vein, at any time during the Data Output at approximately 33.3ms (42ms maximum). Therefore, state, pulling CS high (CS = ↑) causes the part to leave external timing can be used to determine the completion of a the I/O state, abort the output and begin a new conver- conversion cycle. sion. 4) When SCK = HIGH, it is possible to monitor the conver-
SERIAL INTERFACE
sion status by pulling CS low and watching for SDO to The LTC2450 transmits the conversion result and receives go low. This feature is available only in the idle-high the start of conversion command through a synchronous (CPOL = 1) mode. 3-wire interface. This interface can be used during the t1 t2 CS SDO SCK = HI CONVERT SLEEP 2450 F03
Figure 4. Conversion Status Monitoring Mode
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