Datasheet LTC2453 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Ultra-Tiny, Differential, 16-Bit ∆Σ ADC With I2C Interface |
| Pages / Page | 18 / 8 — APPLICATIONS INFORMATION. Reference Voltage Range. I2C INTERFACE. Input … |
| File Format / Size | PDF / 292 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Reference Voltage Range. I2C INTERFACE. Input Voltage Range. The START and STOP Conditions
Model Line for this Datasheet
- LTC2453CDDB#PBF LTC2453CDDB#TRMPBF LTC2453CDDB#TRMPBF LTC2453CDDB#TRPBF LTC2453CDDB#TRPBF LTC2453CTS8#PBF LTC2453CTS8#TRMPBF LTC2453CTS8#TRMPBF LTC2453CTS8#TRPBF LTC2453CTS8#TRPBF LTC2453IDDB#PBF LTC2453IDDB#TRMPBF LTC2453IDDB#TRMPBF LTC2453IDDB#TRPBF LTC2453IDDB#TRPBF LTC2453ITS8#PBF LTC2453ITS8#TRMPBF LTC2453ITS8#TRMPBF LTC2453ITS8#TRPBF LTC2453ITS8#TRPBF
Text Version of Document
LTC2453
APPLICATIONS INFORMATION Reference Voltage Range
capability. For example, if the underrange capability is This converter accepts a truly differential external reference 8LSB, the overrange capability is typically 31 – 8 = 23LSB. voltage. The absolute/common mode voltage range for REF+ and REF– pins covers the entire operating range of
I2C INTERFACE
the device (GND to VCC). For correct converter operation, The LTC2453 communicates through an I2C interface. The V + – REF must be >(2.5V + VREF ). I2C interface is a 2-wire open-drain interface supporting The LTC2453 differential reference input range is 2.5V to multiple devices and masters on a single bus. The con- VCC. For the simplest operation, REF+ can be shorted to nected devices can only pull the data line (SDA) LOW and VCC and REF– can be shorted to GND. never drive it HIGH. SDA must be externally connected to the supply through a pull-up resistor. When the data line
Input Voltage Range
is free, it is HIGH. Data on the I2C bus can be transferred For most applications, V – + – + at rates up to 100kbits/s in the Standard-Mode and up to REF ≤ (VIN , VIN ) ≤ VREF . Under these conditions the output code is given (see Data Format 400kbits/s in the Fast-Mode. The VCC power should not section) as 32768 • (V + – + – be removed from the device when the I2C bus is active to IN – VIN )/(VREF – VREF ) + 32768. The output of the LTC2453 is clamped at a minimum value avoid loading the I2C bus lines through the internal ESD of 0 and clamped at a maximum value of 65535. protection diodes. The LTC2453 includes a proprietary system that can, Each device on the I2C bus is recognized by a unique typically, correctly digitize each input 8LSB above address stored in that device and can operate either as V + – a transmitter or receiver, depending on the function of REF and below VREF , if the LTC2453’s output is not clamped. As an example (Figure 2), if the user desires to the device. In addition to transmitters and receivers, measure a signal slightly below ground, the user could devices can also be considered as masters or slaves when set V – – + + performing data transfers. A master is the device which IN = VREF = GND, and VREF = 5V. If VIN = GND, the output code would be approximately 32768. If V + initiates a data transfer on the bus and generates the IN = GND – 8LSB = –1.22 mV, the output code would be clock signals to permit that transfer. Devices addressed approximately 32760. by the master are considered a slave. The address of the LTC2453 is 0010100. The total amount of overrange and underrange capability is typically 31LSB for a given device. The 31LSB total The LTC2453 can only be addressed as a slave. It can only is distributed between the overrange and underrange transmit the last conversion result. The serial clock line, SCL, is always an input to the LTC2453 and the serial data 32788 line SDA is bidirectional. Figure 3 shows the definition of 32784 the I2C timing. 32780 32776
The START and STOP Conditions
32772 32768 A START (S) condition is generated by transitioning SDA 32764 OUTPUT CODE from HIGH to LOW while SCL is HIGH. The bus is consid- 32760 SIGNALS BELOW ered to be busy after the START condition. When the data 32756 GND transfer is finished, a STOP (P) condition is generated by 32752 transitioning SDA from LOW to HIGH while SCL is HIGH. 32748 –0.001 –0.005 0 0.005 0.001 0.0015 The bus is free after a STOP is generated. START and STOP V + + IN /VREF conditions are always generated by the master. 2453 F02 When the bus is in use, it stays busy if a repeated START
Figure 2. Output Code vs V + – – IN with VIN = 0 and VREF = 0
(Sr) is generated instead of a STOP condition. The repeated 2453fc 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Inputs And References Power Requirements I2C Inputs And Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Application Package Description Revision History Related Parts
APPLICATIONS INFORMATION Reference Voltage Range
capability. For example, if the underrange capability is This converter accepts a truly differential external reference 8LSB, the overrange capability is typically 31 – 8 = 23LSB. voltage. The absolute/common mode voltage range for REF+ and REF– pins covers the entire operating range of
I2C INTERFACE
the device (GND to VCC). For correct converter operation, The LTC2453 communicates through an I2C interface. The V + – REF must be >(2.5V + VREF ). I2C interface is a 2-wire open-drain interface supporting The LTC2453 differential reference input range is 2.5V to multiple devices and masters on a single bus. The con- VCC. For the simplest operation, REF+ can be shorted to nected devices can only pull the data line (SDA) LOW and VCC and REF– can be shorted to GND. never drive it HIGH. SDA must be externally connected to the supply through a pull-up resistor. When the data line
Input Voltage Range
is free, it is HIGH. Data on the I2C bus can be transferred For most applications, V – + – + at rates up to 100kbits/s in the Standard-Mode and up to REF ≤ (VIN , VIN ) ≤ VREF . Under these conditions the output code is given (see Data Format 400kbits/s in the Fast-Mode. The VCC power should not section) as 32768 • (V + – + – be removed from the device when the I2C bus is active to IN – VIN )/(VREF – VREF ) + 32768. The output of the LTC2453 is clamped at a minimum value avoid loading the I2C bus lines through the internal ESD of 0 and clamped at a maximum value of 65535. protection diodes. The LTC2453 includes a proprietary system that can, Each device on the I2C bus is recognized by a unique typically, correctly digitize each input 8LSB above address stored in that device and can operate either as V + – a transmitter or receiver, depending on the function of REF and below VREF , if the LTC2453’s output is not clamped. As an example (Figure 2), if the user desires to the device. In addition to transmitters and receivers, measure a signal slightly below ground, the user could devices can also be considered as masters or slaves when set V – – + + performing data transfers. A master is the device which IN = VREF = GND, and VREF = 5V. If VIN = GND, the output code would be approximately 32768. If V + initiates a data transfer on the bus and generates the IN = GND – 8LSB = –1.22 mV, the output code would be clock signals to permit that transfer. Devices addressed approximately 32760. by the master are considered a slave. The address of the LTC2453 is 0010100. The total amount of overrange and underrange capability is typically 31LSB for a given device. The 31LSB total The LTC2453 can only be addressed as a slave. It can only is distributed between the overrange and underrange transmit the last conversion result. The serial clock line, SCL, is always an input to the LTC2453 and the serial data 32788 line SDA is bidirectional. Figure 3 shows the definition of 32784 the I2C timing. 32780 32776
The START and STOP Conditions
32772 32768 A START (S) condition is generated by transitioning SDA 32764 OUTPUT CODE from HIGH to LOW while SCL is HIGH. The bus is consid- 32760 SIGNALS BELOW ered to be busy after the START condition. When the data 32756 GND transfer is finished, a STOP (P) condition is generated by 32752 transitioning SDA from LOW to HIGH while SCL is HIGH. 32748 –0.001 –0.005 0 0.005 0.001 0.0015 The bus is free after a STOP is generated. START and STOP V + + IN /VREF conditions are always generated by the master. 2453 F02 When the bus is in use, it stays busy if a repeated START
Figure 2. Output Code vs V + – – IN with VIN = 0 and VREF = 0
(Sr) is generated instead of a STOP condition. The repeated 2453fc 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Inputs And References Power Requirements I2C Inputs And Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Application Package Description Revision History Related Parts
