Datasheet LTC2460, LTC2462 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Ultra-Tiny, 16-Bit ΔΣ ADCs with 10ppm/°C Max Precision Reference |
| Pages / Page | 22 / 7 — block DiagraM. Figure 1. Functional Block Diagram. applicaTions … |
| File Format / Size | PDF / 317 Kb |
| Document Language | English |
block DiagraM. Figure 1. Functional Block Diagram. applicaTions inForMaTion. CONVERTER OPERATION. Converter Operation Cycle
Model Line for this Datasheet
Text Version of Document
LTC2460/LTC2462
block DiagraM
1 2 12 REFOUT COMP VCC 3 CS INTERNAL ∆Σ A/D 5 REFERENCE SPI SCK 9 IN+ CONVERTER INTERFACE 6 SDO (IN) DECIMATING – 4 SINC FILTER SDI ∆Σ A/D 10 IN– CONVERTER (GND) INTERNAL OSCILLATOR REF– 7,11,13 (DD PACKAGE) GND 8 24602 BD ( ) PARENTHESIS INDICATE LTC2460
Figure 1. Functional Block Diagram applicaTions inForMaTion CONVERTER OPERATION
POWER-ON RESET
Converter Operation Cycle
CONVERT The LTC2460/LTC2462 are low power, delta sigma, ana- log to digital converters with a simple SPI interface (see SLEEP/NAP Figure 1). The LTC2462 has a fully differential input while the LTC2460 is single-ended. Both are pin and software compatible. Their operation is composed of three distinct NO CS = LOW? states: CONVERT, SLEEP/NAP, and DATA INPUT/OUTPUT. The operation begins with the CONVERT state (see Fig- ure 2). Once the conversion is finished, the converter YES automatically powers down (NAP) or under user control, both the converter and reference are powered down DATA INPUT/OUTPUT (SLEEP). The conversion result is held in a static register while the device is in this state. The cycle concludes with the DATA INPUT/OUTPUT state. Once all 16-bits are read 16TH FALLING NO YES or an abort is initiated the device begins a new conversion. EDGE OF SCK OR 24602 F02 CS = HIGH? The CONVERT state duration is determined by the LTC2460/ LTC2462 conversion time (nominally 16.6 milliseconds). Once started, this operation can not be aborted except by a
Figure 2. LTC2460/LTC2462 State Transition Diagram
low power supply condition (VCC < 2.1V) which generates While in the SLEEP/NAP state, when chip select input is an internal power-on reset signal. HIGH (CS = HIGH), the LTC2460/LTC2462’s converters After the completion of a conversion, the LTC2460/LTC2462 are powered down. This reduces the supply current by enters the SLEEP/NAP state and remains there until the approximately 50%. While in the Nap state the reference chip select is LOW (CS = LOW). Following this condition, remains powered up. In order to power down the reference the ADC transitions into the DATA INPUT/OUTPUT state. in addition to the converter, the user can select the SLEEP 24602fa 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Analog Inputs Power Requirements Digital Inputs and Digital Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Applications Information Package Description Revision History Typical Application Related Parts
block DiagraM
1 2 12 REFOUT COMP VCC 3 CS INTERNAL ∆Σ A/D 5 REFERENCE SPI SCK 9 IN+ CONVERTER INTERFACE 6 SDO (IN) DECIMATING – 4 SINC FILTER SDI ∆Σ A/D 10 IN– CONVERTER (GND) INTERNAL OSCILLATOR REF– 7,11,13 (DD PACKAGE) GND 8 24602 BD ( ) PARENTHESIS INDICATE LTC2460
Figure 1. Functional Block Diagram applicaTions inForMaTion CONVERTER OPERATION
POWER-ON RESET
Converter Operation Cycle
CONVERT The LTC2460/LTC2462 are low power, delta sigma, ana- log to digital converters with a simple SPI interface (see SLEEP/NAP Figure 1). The LTC2462 has a fully differential input while the LTC2460 is single-ended. Both are pin and software compatible. Their operation is composed of three distinct NO CS = LOW? states: CONVERT, SLEEP/NAP, and DATA INPUT/OUTPUT. The operation begins with the CONVERT state (see Fig- ure 2). Once the conversion is finished, the converter YES automatically powers down (NAP) or under user control, both the converter and reference are powered down DATA INPUT/OUTPUT (SLEEP). The conversion result is held in a static register while the device is in this state. The cycle concludes with the DATA INPUT/OUTPUT state. Once all 16-bits are read 16TH FALLING NO YES or an abort is initiated the device begins a new conversion. EDGE OF SCK OR 24602 F02 CS = HIGH? The CONVERT state duration is determined by the LTC2460/ LTC2462 conversion time (nominally 16.6 milliseconds). Once started, this operation can not be aborted except by a
Figure 2. LTC2460/LTC2462 State Transition Diagram
low power supply condition (VCC < 2.1V) which generates While in the SLEEP/NAP state, when chip select input is an internal power-on reset signal. HIGH (CS = HIGH), the LTC2460/LTC2462’s converters After the completion of a conversion, the LTC2460/LTC2462 are powered down. This reduces the supply current by enters the SLEEP/NAP state and remains there until the approximately 50%. While in the Nap state the reference chip select is LOW (CS = LOW). Following this condition, remains powered up. In order to power down the reference the ADC transitions into the DATA INPUT/OUTPUT state. in addition to the converter, the user can select the SLEEP 24602fa 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Analog Inputs Power Requirements Digital Inputs and Digital Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Applications Information Package Description Revision History Typical Application Related Parts
