Datasheet LTC2486 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 16-Bit 2-/4-Channel ∆Σ ADC with PGA and Easy Drive Input Current Cancellation |
| Pages / Page | 36 / 5 — DIGITAL. INPUTS AND DIGITAL OUTPUTS The. denotes the specifications which … |
| File Format / Size | PDF / 502 Kb |
| Document Language | English |
DIGITAL. INPUTS AND DIGITAL OUTPUTS The. denotes the specifications which apply over the
Model Line for this Datasheet
Text Version of Document
LTC2486
DIGITAL INPUTS AND DIGITAL OUTPUTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range (Note 16) l 10 1000 kHz tHEO External Oscillator High Period l 0.125 50 µs tLEO External Oscillator Low Period l 0.125 50 µs tCONV_1 Conversion Time for 1x Speed Mode 50Hz Mode l 157.2 160.3 163.5 ms 60Hz Mode l 131 133.6 136.3 ms Simultaneous 50/60Hz Mode l 144.1 146.9 149.9 ms External Oscillator 41036/fEOSC (in kHz) ms tCONV_2 Conversion Time for 2x Speed Mode 50Hz Mode l 78.7 80.3 81.9 ms 60Hz Mode l 65.6 66.9 68.2 ms Simultaneous 50/60Hz Mode l 72.2 73.6 75.1 ms External Oscillator 20556/fEOSC (in kHz) ms fISCK Internal SCK Frequency Internal Oscillator (Notes 10, 17) 38.4 kHz External Oscillator (Notes 10, 11, 15) fEOSC/8 kHz DISCK Internal SCK Duty Cycle (Notes 10, 17) l 45 55 % fESCK External SCK Frequency Range (Notes 10, 11, 15) l 4000 kHz tLESCK External SCK Low Period (Notes 10, 11, 15) l 125 ns tHESCK External SCK High Period (Notes 10, 11, 15) l 125 ns tDOUT_ISCK Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 17) l 0.61 0.625 0.64 ms External Oscillator (Notes 10, 11, 15) 192/fEOSC (in kHz) ms tDOUT_ESCK External SCK 24-Bit Data Output Time (Notes 10, 11, 15) 24/fESCK (in kHz) ms t1 CS↓ to SDO Low l 0 200 ns t2 CS↑ to SDO High Z l 0 200 ns t3 CS↓ to SCK↓ Internal SCK Mode l 0 200 ns t4 CS↓ to SCK↑ External SCK Mode l 50 ns tKQMAX SCK↓ to SDO Valid l 200 ns tKQMIN SDO Hold After SCK↓ (Note 5) l 15 ns t5 SCK Set-Up Before CS↓ l 50 ns t7 SDI Setup Before SCK↑ (Note 5) l 100 ns t8 SDI Hold After SCK↑ (Note 5) l 100 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 9:
Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC = may cause permanent damage to the device. Exposure to any Absolute 280kHz ±2% (external oscillator). Maximum Rating condition for extended periods may affect device
Note 10:
The SCK can be configured in external SCK mode or internal SCK reliability and lifetime. mode. In external SCK mode, the SCK pin is used as a digital input and the
Note 2:
All voltage values are with respect to GND. driving clock is fESCK. In the internal SCK mode, the SCK pin is used as a
Note 3:
Unless otherwise specified: digital output and the output clock signal during the data output is fISCK. V
Note 11:
The external oscillator is connected to the f CC = 2.7V to 5.5V O pin. The external V oscillator frequency, f REFCM = VREF/2, FS = 0.5VREF/Gain EOSC, is expressed in kHz. V
Note 12:
The converter uses its internal oscillator. IN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2, where IN+ and IN– are the selected input channels.
Note 13:
The output noise includes the contribution of the internal
Note 4:
Use internal conversion clock or external conversion clock source calibration operations. with f
Note 14:
Guaranteed by design and test correlation. EOSC = 307.2kHz unless other wise specified.
Note 5:
Guaranteed by design, not subject to test.
Note 15:
The converter is in external SCK mode of operation such that the
Note 6:
Integral nonlinearity is defined as the deviation of a code from a SCK pin is used as a digital input. The frequency of the clock signal driving straight line passing through the actual endpoints of the transfer curve. SCK during the data output is fESCK and is expressed in Hz. The deviation is measured from the center of the quantization band.
Note 16:
Refer to Applications Information section for performance vs
Note 7:
50Hz mode (internal oscillator) or f data rate graphs. EOSC = 256kHz ±2% (external oscillator).
Note 17:
The converter in internal SCK mode of operation such that the
Note 8:
60Hz mode (internal oscillator) or f SCK pin is used as a digital output. EOSC = 307.2kHz ±2% (external oscillator).
Note 18:
For VCC < 3V, VIH is 2.5V for pin fO. 2486fe For more information www.linear.com/LTC2486 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics (Normal Speed) Electrical Characteristics (2x Speed) Converter Characteristics Analog Input and Reference Digital Inputs and Digital Outputs Power Requirements Typical Performance Characteristics Pin Functions Functional Block Diagram Test Circuits Timing Diagrams Applications Information Package Description Revision History Typical Application Related Parts
DIGITAL INPUTS AND DIGITAL OUTPUTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range (Note 16) l 10 1000 kHz tHEO External Oscillator High Period l 0.125 50 µs tLEO External Oscillator Low Period l 0.125 50 µs tCONV_1 Conversion Time for 1x Speed Mode 50Hz Mode l 157.2 160.3 163.5 ms 60Hz Mode l 131 133.6 136.3 ms Simultaneous 50/60Hz Mode l 144.1 146.9 149.9 ms External Oscillator 41036/fEOSC (in kHz) ms tCONV_2 Conversion Time for 2x Speed Mode 50Hz Mode l 78.7 80.3 81.9 ms 60Hz Mode l 65.6 66.9 68.2 ms Simultaneous 50/60Hz Mode l 72.2 73.6 75.1 ms External Oscillator 20556/fEOSC (in kHz) ms fISCK Internal SCK Frequency Internal Oscillator (Notes 10, 17) 38.4 kHz External Oscillator (Notes 10, 11, 15) fEOSC/8 kHz DISCK Internal SCK Duty Cycle (Notes 10, 17) l 45 55 % fESCK External SCK Frequency Range (Notes 10, 11, 15) l 4000 kHz tLESCK External SCK Low Period (Notes 10, 11, 15) l 125 ns tHESCK External SCK High Period (Notes 10, 11, 15) l 125 ns tDOUT_ISCK Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 17) l 0.61 0.625 0.64 ms External Oscillator (Notes 10, 11, 15) 192/fEOSC (in kHz) ms tDOUT_ESCK External SCK 24-Bit Data Output Time (Notes 10, 11, 15) 24/fESCK (in kHz) ms t1 CS↓ to SDO Low l 0 200 ns t2 CS↑ to SDO High Z l 0 200 ns t3 CS↓ to SCK↓ Internal SCK Mode l 0 200 ns t4 CS↓ to SCK↑ External SCK Mode l 50 ns tKQMAX SCK↓ to SDO Valid l 200 ns tKQMIN SDO Hold After SCK↓ (Note 5) l 15 ns t5 SCK Set-Up Before CS↓ l 50 ns t7 SDI Setup Before SCK↑ (Note 5) l 100 ns t8 SDI Hold After SCK↑ (Note 5) l 100 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 9:
Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC = may cause permanent damage to the device. Exposure to any Absolute 280kHz ±2% (external oscillator). Maximum Rating condition for extended periods may affect device
Note 10:
The SCK can be configured in external SCK mode or internal SCK reliability and lifetime. mode. In external SCK mode, the SCK pin is used as a digital input and the
Note 2:
All voltage values are with respect to GND. driving clock is fESCK. In the internal SCK mode, the SCK pin is used as a
Note 3:
Unless otherwise specified: digital output and the output clock signal during the data output is fISCK. V
Note 11:
The external oscillator is connected to the f CC = 2.7V to 5.5V O pin. The external V oscillator frequency, f REFCM = VREF/2, FS = 0.5VREF/Gain EOSC, is expressed in kHz. V
Note 12:
The converter uses its internal oscillator. IN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2, where IN+ and IN– are the selected input channels.
Note 13:
The output noise includes the contribution of the internal
Note 4:
Use internal conversion clock or external conversion clock source calibration operations. with f
Note 14:
Guaranteed by design and test correlation. EOSC = 307.2kHz unless other wise specified.
Note 5:
Guaranteed by design, not subject to test.
Note 15:
The converter is in external SCK mode of operation such that the
Note 6:
Integral nonlinearity is defined as the deviation of a code from a SCK pin is used as a digital input. The frequency of the clock signal driving straight line passing through the actual endpoints of the transfer curve. SCK during the data output is fESCK and is expressed in Hz. The deviation is measured from the center of the quantization band.
Note 16:
Refer to Applications Information section for performance vs
Note 7:
50Hz mode (internal oscillator) or f data rate graphs. EOSC = 256kHz ±2% (external oscillator).
Note 17:
The converter in internal SCK mode of operation such that the
Note 8:
60Hz mode (internal oscillator) or f SCK pin is used as a digital output. EOSC = 307.2kHz ±2% (external oscillator).
Note 18:
For VCC < 3V, VIH is 2.5V for pin fO. 2486fe For more information www.linear.com/LTC2486 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics (Normal Speed) Electrical Characteristics (2x Speed) Converter Characteristics Analog Input and Reference Digital Inputs and Digital Outputs Power Requirements Typical Performance Characteristics Pin Functions Functional Block Diagram Test Circuits Timing Diagrams Applications Information Package Description Revision History Typical Application Related Parts
