Datasheet LTC2488 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 16-Bit 2-/4-Channel ΔΣ ADC with Easy Drive Input Current Cancellation |
| Pages / Page | 30 / 8 — PIN FUNCTIONS. FO (Pin 1):. GND (Pin 6):. COM (Pin 7):. SDI (Pin 2):. SCK … |
| File Format / Size | PDF / 399 Kb |
| Document Language | English |
PIN FUNCTIONS. FO (Pin 1):. GND (Pin 6):. COM (Pin 7):. SDI (Pin 2):. SCK (Pin 3):. CH0 to CH3 (Pins 8-11):. VCC (Pin 12):. CS (Pin 4):
Model Line for this Datasheet
Text Version of Document
LTC2488
PIN FUNCTIONS FO (Pin 1):
Frequency Control Pin. Digital input that controls the conversion is in progress this pin is HIGH; once the the internal conversion clock rate. When FO is connected to conversion is complete SDO goes low. The conversion ground, the converter uses its internal oscillator running status is monitored by pulling CS LOW. at 307.2kHz. The conversion clock may also be overridden
GND (Pin 6):
Ground. Connect this pin to a common ground by driving the FO pin with an external clock in order to plane through a low impedance connection. change the output rate and the digital filter rejection null.
COM (Pin 7):
The common negative input (IN–) for all
SDI (Pin 2):
Serial Data Input. This pin is used to select single ended multiplexer configurations. The voltage on the input channel. The serial data input is applied under CH0 to CH3 and COM pins can have any value between control of the serial clock (SCK) during the data output/ GND – 0.3V to V input operation. The first conversion following a new input CC + 0.3V. Within these limits, the two selected inputs (IN+ and IN–) provide a bipolar input range is valid. (VIN = IN+ – IN–) from –0.5 • VREF to 0.5 • VREF. Outside
SCK (Pin 3):
Bidirectional, Digital I/O, Clock Pin. In Internal this input range, the converter produces unique over-range Serial Clock Operation mode, SCK is generated internally and under-range output codes. and is seen as an output on the SCK pin. In External Serial
CH0 to CH3 (Pins 8-11):
Analog Inputs. May be pro- Clock Operation mode, the digital I/O clock is externally grammed for single-ended or differential mode. applied to the SCK pin. The Serial Clock operation mode is determined by the logic level applied to the SCK pin at
VCC (Pin 12):
Positive Supply Voltage. Bypass to GND with power up and during the most recent falling edge of CS. a 10µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor as close to the part as possible.
CS (Pin 4):
Active LOW Chip Select. A LOW on this pin enables the digital input/output and wakes up the ADC. Following
REF+ (Pin 13), REF– (Pin 14):
Differential Reference Input. each conversion, the ADC automatically enters the Sleep The voltage on these pins can have any value between mode and remains in this low power state as long as CS GND and VCC as long as the reference positive input, REF+, is HIGH. A LOW-to-HIGH transition on CS during the data remains more positive than the negative reference input, output aborts the data transfer and starts a new conversion. REF–, by at least 0.1V. The differential voltage (VREF = REF+ – REF–) sets the fullscale range for all input channels.
SDO (Pin 5):
Three-State Digital Output. During the data output period, this pin is used as the serial data output.
Exposed Pad (Pin 15):
Ground. This pin is ground and When the chip select pin is HIGH, the SDO pin is in a high must be soldered to the PCB ground plane. For prototyping impedance state. During the conversion and sleep periods, purposes, this pin may remain floating. this pin is used as the conversion status output. When 2488fb 8 For more information www.linear.com/LTC2488
PIN FUNCTIONS FO (Pin 1):
Frequency Control Pin. Digital input that controls the conversion is in progress this pin is HIGH; once the the internal conversion clock rate. When FO is connected to conversion is complete SDO goes low. The conversion ground, the converter uses its internal oscillator running status is monitored by pulling CS LOW. at 307.2kHz. The conversion clock may also be overridden
GND (Pin 6):
Ground. Connect this pin to a common ground by driving the FO pin with an external clock in order to plane through a low impedance connection. change the output rate and the digital filter rejection null.
COM (Pin 7):
The common negative input (IN–) for all
SDI (Pin 2):
Serial Data Input. This pin is used to select single ended multiplexer configurations. The voltage on the input channel. The serial data input is applied under CH0 to CH3 and COM pins can have any value between control of the serial clock (SCK) during the data output/ GND – 0.3V to V input operation. The first conversion following a new input CC + 0.3V. Within these limits, the two selected inputs (IN+ and IN–) provide a bipolar input range is valid. (VIN = IN+ – IN–) from –0.5 • VREF to 0.5 • VREF. Outside
SCK (Pin 3):
Bidirectional, Digital I/O, Clock Pin. In Internal this input range, the converter produces unique over-range Serial Clock Operation mode, SCK is generated internally and under-range output codes. and is seen as an output on the SCK pin. In External Serial
CH0 to CH3 (Pins 8-11):
Analog Inputs. May be pro- Clock Operation mode, the digital I/O clock is externally grammed for single-ended or differential mode. applied to the SCK pin. The Serial Clock operation mode is determined by the logic level applied to the SCK pin at
VCC (Pin 12):
Positive Supply Voltage. Bypass to GND with power up and during the most recent falling edge of CS. a 10µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor as close to the part as possible.
CS (Pin 4):
Active LOW Chip Select. A LOW on this pin enables the digital input/output and wakes up the ADC. Following
REF+ (Pin 13), REF– (Pin 14):
Differential Reference Input. each conversion, the ADC automatically enters the Sleep The voltage on these pins can have any value between mode and remains in this low power state as long as CS GND and VCC as long as the reference positive input, REF+, is HIGH. A LOW-to-HIGH transition on CS during the data remains more positive than the negative reference input, output aborts the data transfer and starts a new conversion. REF–, by at least 0.1V. The differential voltage (VREF = REF+ – REF–) sets the fullscale range for all input channels.
SDO (Pin 5):
Three-State Digital Output. During the data output period, this pin is used as the serial data output.
Exposed Pad (Pin 15):
Ground. This pin is ground and When the chip select pin is HIGH, the SDO pin is in a high must be soldered to the PCB ground plane. For prototyping impedance state. During the conversion and sleep periods, purposes, this pin may remain floating. this pin is used as the conversion status output. When 2488fb 8 For more information www.linear.com/LTC2488
