Datasheet LTM9013 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 300MHz Wideband Receiver |
| Pages / Page | 38 / 9 — pin FuncTions. Supply Pins. +IN_Q, –IN_Q (Pins E4, E5):. CC1 (Pin B7):. … |
| File Format / Size | PDF / 978 Kb |
| Document Language | English |
pin FuncTions. Supply Pins. +IN_Q, –IN_Q (Pins E4, E5):. CC1 (Pin B7):. GAIN_I (Pin C12):. CC2 (Pins A2, A3, A12, A13, D1, D12):
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Text Version of Document
LTM9013
pin FuncTions Supply Pins +IN_Q, –IN_Q (Pins E4, E5):
Channel Q Signal Input. This
V
is a differential input that drives the Amplifier. It has an
CC1 (Pin B7):
Analog 5V Supply for Demodulator and Amplifiers. The specified operating range is 4.75V to 5.25V. internally generated DC bias. Series blocking capacitors The voltage on this pin provides power for the demodulator are required between these pins and +OUT_Q, –OUT_Q. and amplifier stages only and is internally bypassed to GND.
GAIN_I (Pin C12):
I Channel Gain Control Input. This is
V
an input that controls the gain of the amplifier. This pin is
CC2 (Pins A2, A3, A12, A13, D1, D12):
Analog 3.3V Sup- ply for Amplifiers. The specified operating range is 2.7V to internally pulled low with 10kΩ to GND. The gain control 3.6V. V slope is approximately 32dB/V with a gain control range CC2 is internally bypassed to GND. of 0.1V to 1.1V.
VDD (Pins J6, J9):
Analog 1.8V Supply for ADC. The specified operating range is 1.74V to 1.9V. V
GAIN_Q (Pin C1):
Q Channel Gain Control Input. This is DD is internally bypassed to GND. an input that controls the gain of the amplifier. This pin is internally pulled low with 10kΩ to GND. The gain control
OVDD (Pins N5, N10):
Positive 1.8V Supply for the Digital slope is approximately 32dB/V with a gain control range Output Drivers. The specified operating range is 1.74V to of 0.1V to 1.1V. 1.9V. OVDD is internally bypassed to GND.
CLK+, CLK– (Pins J5, K5):
ADC Clock Input. Conversion
GND:
Analog Ground. See Pin Configuration table for pin starts on the rising edge of CLK+. locations.
IP2_I (Pin C10):
IP2 Adjustment Pin for I Channel.
Analog Inputs IP2_Q (Pin D10):
IP2 Adjustment Pin for Q Channel.
RF (Pin A10):
RF Input Pin. This is a single-ended 50Ω
REF (Pin D8):
Voltage Reference Input for Analog Control terminated input. No external matching network is required Voltage Pins. for the 1.5GHz to 2.7GHz band. An external series inductor (and/or shunt capacitor) may be required for impedance
SENSE (Pin J8):
ADC Reference Programming Pin. Con- transformation to 50Ω in the band from 700MHz to 1.5GHz, necting SENSE to VDD selects the internal reference and or for the band from 2.7GHz to 4GHz (see Figure 2). If the a 1.32V input range. RF source is not DC blocked, a series blocking capacitor
Analog Outputs
should be used. Otherwise, damage to the IC may result.
+OUT_I, –OUT_I (Pins F10, F11):
Channel I Signal Output.
LO+, LO– (Pins A6, A5):
Local Oscillator Input Pins. This is a This is a differential output from the demodulator. The DC differential 50Ω terminated input. An external series induc- bias point is V tor (and/or shunt capacitor) may be required for impedance CC1 – 1.5V for each pin. These pins must have an external 100Ω or inductor pull-up to V transformation to 50Ω in the band from 700MHz to 1.5GHz, CC1. Series blocking capacitors are required between these pins and or for the band from 2.7GHz to 4GHz (see Figure 4). If the +IN_I, –IN_I. LO source is not DC blocked, a series blocking capacitor must be used. Otherwise, damage to the IC may result.
+OUT_Q, –OUT_Q (Pins F4, F5):
Channel Q Signal Output. This is a differential output from the demodulator. The DC
+IN_I, –IN_I (Pins E10, E11):
Channel I Signal Input. This bias point is V is a differential input that drives the amplifier. It has an CC1 – 1.5V for each pin. These pins must have an external 100Ω or inductor pull-up to V internally generated DC bias. Series blocking capacitors CC1. Series blocking capacitors are required between these pins and are required between these pins and +OUT_I, –OUT_I. +IN_Q, –IN_Q. 9013fa For more information www.linear.com/LTM9013 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Dynamic Accuracy Analog Inputs and Outputs Digital Inputs and Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
pin FuncTions Supply Pins +IN_Q, –IN_Q (Pins E4, E5):
Channel Q Signal Input. This
V
is a differential input that drives the Amplifier. It has an
CC1 (Pin B7):
Analog 5V Supply for Demodulator and Amplifiers. The specified operating range is 4.75V to 5.25V. internally generated DC bias. Series blocking capacitors The voltage on this pin provides power for the demodulator are required between these pins and +OUT_Q, –OUT_Q. and amplifier stages only and is internally bypassed to GND.
GAIN_I (Pin C12):
I Channel Gain Control Input. This is
V
an input that controls the gain of the amplifier. This pin is
CC2 (Pins A2, A3, A12, A13, D1, D12):
Analog 3.3V Sup- ply for Amplifiers. The specified operating range is 2.7V to internally pulled low with 10kΩ to GND. The gain control 3.6V. V slope is approximately 32dB/V with a gain control range CC2 is internally bypassed to GND. of 0.1V to 1.1V.
VDD (Pins J6, J9):
Analog 1.8V Supply for ADC. The specified operating range is 1.74V to 1.9V. V
GAIN_Q (Pin C1):
Q Channel Gain Control Input. This is DD is internally bypassed to GND. an input that controls the gain of the amplifier. This pin is internally pulled low with 10kΩ to GND. The gain control
OVDD (Pins N5, N10):
Positive 1.8V Supply for the Digital slope is approximately 32dB/V with a gain control range Output Drivers. The specified operating range is 1.74V to of 0.1V to 1.1V. 1.9V. OVDD is internally bypassed to GND.
CLK+, CLK– (Pins J5, K5):
ADC Clock Input. Conversion
GND:
Analog Ground. See Pin Configuration table for pin starts on the rising edge of CLK+. locations.
IP2_I (Pin C10):
IP2 Adjustment Pin for I Channel.
Analog Inputs IP2_Q (Pin D10):
IP2 Adjustment Pin for Q Channel.
RF (Pin A10):
RF Input Pin. This is a single-ended 50Ω
REF (Pin D8):
Voltage Reference Input for Analog Control terminated input. No external matching network is required Voltage Pins. for the 1.5GHz to 2.7GHz band. An external series inductor (and/or shunt capacitor) may be required for impedance
SENSE (Pin J8):
ADC Reference Programming Pin. Con- transformation to 50Ω in the band from 700MHz to 1.5GHz, necting SENSE to VDD selects the internal reference and or for the band from 2.7GHz to 4GHz (see Figure 2). If the a 1.32V input range. RF source is not DC blocked, a series blocking capacitor
Analog Outputs
should be used. Otherwise, damage to the IC may result.
+OUT_I, –OUT_I (Pins F10, F11):
Channel I Signal Output.
LO+, LO– (Pins A6, A5):
Local Oscillator Input Pins. This is a This is a differential output from the demodulator. The DC differential 50Ω terminated input. An external series induc- bias point is V tor (and/or shunt capacitor) may be required for impedance CC1 – 1.5V for each pin. These pins must have an external 100Ω or inductor pull-up to V transformation to 50Ω in the band from 700MHz to 1.5GHz, CC1. Series blocking capacitors are required between these pins and or for the band from 2.7GHz to 4GHz (see Figure 4). If the +IN_I, –IN_I. LO source is not DC blocked, a series blocking capacitor must be used. Otherwise, damage to the IC may result.
+OUT_Q, –OUT_Q (Pins F4, F5):
Channel Q Signal Output. This is a differential output from the demodulator. The DC
+IN_I, –IN_I (Pins E10, E11):
Channel I Signal Input. This bias point is V is a differential input that drives the amplifier. It has an CC1 – 1.5V for each pin. These pins must have an external 100Ω or inductor pull-up to V internally generated DC bias. Series blocking capacitors CC1. Series blocking capacitors are required between these pins and are required between these pins and +OUT_I, –OUT_I. +IN_Q, –IN_Q. 9013fa For more information www.linear.com/LTM9013 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Dynamic Accuracy Analog Inputs and Outputs Digital Inputs and Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
