Datasheet LT1944 (Analog Devices) - 7

ManufacturerAnalog Devices
DescriptionDual Micropower Step-Up DC/DC Converter
Pages / Page8 / 7 — TYPICAL APPLICATIO S. 2-Cell Dual Output (3.3V, 5V) Boost Converter. …
File Format / SizePDF / 168 Kb
Document LanguageEnglish

TYPICAL APPLICATIO S. 2-Cell Dual Output (3.3V, 5V) Boost Converter. 2-Cell to 5V Efficiency. 2-Cell to 3.3V Efficiency

TYPICAL APPLICATIO S 2-Cell Dual Output (3.3V, 5V) Boost Converter 2-Cell to 5V Efficiency 2-Cell to 3.3V Efficiency

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LT1944
U TYPICAL APPLICATIO S 2-Cell Dual Output (3.3V, 5V) Boost Converter
L1 4.7 V µH D1 IN 5V 1.8V 40mA TO 3V 8 10 4.7pF 1M VIN SW1 2 1 SHDN1 FB1 C1 LT1944 C2 4.7µF 10µF 4 5 SHDN2 FB2 324k GND PGND PGND SW2 3 7 9 6 604k C1: TAIYO YUDEN JMK212BJ475 (408) 573-4150 C3 4.7pF 1M C2, C3: TAIYO YUDEN JMK316BJ106 (408) 573-4150 10µF L2 D1, D2: ON SEMI MBR0520 (800) 282-9855 4.7µH D2 3.3V L1, L2: MURATA LQH3C4R7 (814) 237-1431 80mA 1944 TA02
2-Cell to 5V Efficiency 2-Cell to 3.3V Efficiency
90 90 85 85 VIN = 3V VIN = 3V 80 80 75 VIN = 1.8V 75 70 70 VIN = 1.8V 65 EFFICIENCY (%) 65 EFFICIENCY (%) 60 60 55 55 50 50 0.1 1 10 100 0.1 1 10 100 LOAD CURRENT (mA) LOAD CURRENT (mA) 1944 TA02a 1944 TA02b
U PACKAGE DESCRIPTIO MS10 Package 10-Lead Plastic MSOP
(LTC DWG # 05-08-1661) 0.118 ± 0.004* 0.043 0.034 (3.00 ± 0.102) (1.10) (0.86) 10 9 8 7 6 MAX REF 0.007 0° – 6° TYP (0.18) SEATING 0.193 ± 0.006 0.118 ± 0.004** PLANE (3.00 ± 0.102) 0.021 ± 0.006 0.007 – 0.011 0.005 ± 0.002 (4.90 ± 0.15) (0.53 ± 0.015) (0.17 – 0.27) (0.13 ± 0.05) 0.0197 MSOP (MS10) 1100 (0.50) BSC 1 2 3 4 5 * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7