LT3494/LT3494A APPLICATIONS INFORMATION the CAP pin will improve effi ciency and lower the stress GND placed on the internal Schottky diode. Board Layout Considerations SW CAP As with all switching regulators, careful attention must be GND VOUT GND paid to the PCB board layout and component placement. V FB To maximize effi ciency, switch rise and fall times are made CC as short as possible. To prevent electromagnetic interfer- CTRL SHDN ence (EMI) problems, proper layout of the high frequency switching path is essential. The voltage signal of the SW pin has sharp rising and falling edges. Minimize the length and 3494 F04 area of all traces connected to the SW pin and always use CTRL SHDN a ground plane under the switching regulator to minimize VIAS TO GROUND PLANE REQUIRED interplane coupling. In addition, the FB connection for TO IMPROVE THERMAL PERFORMANCE the feedback resistor R1 should be tied directly from the Figure 4. Recommended Layout Vout pin to the FB pin and be kept as short as possible, ensuring a clean, noise-free connection. Recommended component placement is shown in Figure 4. TYPICAL APPLICATIONS L1 3.6V to 16V Effi ciency 15μH VIN 90 280 3V TO 4.2V V C2 1 8 C1 IN = 3.6V LOAD FROM 4.7μF 0.22μF CAPACITOR SW CAP 80 240 3 7 VCC VOUT VOUT LOAD FROM POWER LOSS (mW) 70 200 C3 V LT3494 R1 OUT 2.2μF 5 6 TURN ON/OFF SHDN FB 60 160 4 2 V CTRL GND OUT DIMMING 50 120 3494 F05 EFFICIENCY (%) C1, C2: X5R OR X7R WITH SUFFICIENT VOLTAGE RATING 40 80 C3: MURATA GRM31MR71E225K L1: MURATA LQH32CN150K53 30 40 Figure 5. One Li-Ion Cell Input Boost Converter with the LT3494 20 0 0.1 1 10 100 R1 VALUE REQUIREDMAXIMUM OUTPUT CURRENT AT LOAD CURRENT (mA) VOUT(M Ω )3V INPUT (mA) 3494 TA01c 25 3.57 8.6 24 3.40 9.3 23 3.24 10.0 22 3.09 10.6 21 2.94 11.3 20 2.80 12.1 19 2.67 12.9 18 2.49 13.6 17 2.37 14.8 16 2.21 16.0 15 2.05 17.2 3494fb 10