Datasheet LT3959 (Analog Devices) - 9

ManufacturerAnalog Devices
DescriptionWide Input Voltage Range Boost/SEPIC/Inverting Converter with 6A, 40V Switch
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applicaTions inForMaTion Main Control Loop. Programming Turn-On and Turn-Off Thresholds with. EN/UVLO Pin

applicaTions inForMaTion Main Control Loop Programming Turn-On and Turn-Off Thresholds with EN/UVLO Pin

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LT3959
applicaTions inForMaTion Main Control Loop
comparator A2 performs the noninverting amplification The LT3959 uses a fixed frequency, current mode control from FBX to VC. scheme to provide excellent line and load regulation. The LT3959 has overvoltage protection functions to Operation can be best understood by referring to the Block protect the converter from excessive output voltage Diagram in Figure 1. overshoot during start-up or recovery from a short-circuit The start of each oscillator cycle sets the SR latch (SR1) condition. An overvoltage comparator A11 (with 40mV and turns on the internal power MOSFET switch M1 through hysteresis) senses when the FBX pin voltage exceeds the driver G2. The switch current flows through the internal positive regulated voltage (1.6V) by 7.5% and turns off current sensing resistor R M1. Similarly, an overvoltage comparator A12 (with 20mV SENSE and generates a voltage proportional to the switch current. This current sense hysteresis) senses when the FBX pin voltage exceeds the voltage V negative regulated voltage (–0.8V) by 7.5% and turns ISENSE (amplified by A5) is added to a stabilizing slope compensation ramp and the resulting sum (SLOPE) off M1. Both reset pulses are sent to the main RS latch is fed into the positive terminal of the PWM comparator A7. (SR1) through G6 and G5. The internal power MOSFET When SLOPE exceeds the level at the negative input of A7 switch M1 is actively held off for the duration of an output (V overvoltage condition. C pin), SR1 is reset, turning off the power switch. The level at the negative input of A7 is set by the error amplifier A1 (or A2) and is an amplified version of the difference
Programming Turn-On and Turn-Off Thresholds with
between the feedback voltage (FBX pin) and the reference
EN/UVLO Pin
voltage (1.6V or –0.8V, depending on the configuration). The EN/UVLO pin controls whether the LT3959 is enabled In this manner, the error amplifier sets the correct peak or is in shutdown state. A micropower 1.22V reference, a switch current level to keep the output in regulation. comparator A10 and controllable current source IS1 allow The LT3959 has a switch current limit function. The cur- the user to accurately program the supply voltage at which rent sense voltage is input to the current limit comparator the IC turns on and off. The falling value can be accurately A6. If the SENSE voltage is higher than the sense current set by the resistor dividers R3 and R4. When EN/UVLO limit threshold V is above 0.7V, and below the 1.22V threshold, the small SENSE(MAX) (45mV, typical), A6 will reset SR1 and turn off M1 immediately. pull-down current source IS1 (typical 2.2µA) is active. The LT3959 is capable of generating either positive or The purpose of this current is to allow the user to program negative output voltage with a single FBX pin. It can be the rising hysteresis. The Block Diagram of the comparator configured as a boost or SEPIC converter to generate and the external resistors is shown in Figure 1. The typical positive output voltage, or as an inverting converter to falling threshold voltage and rising threshold voltage can generate negative output voltage. When configured as be calculated by the following equations: a SEPIC converter, as shown in Figure 1, the FBX pin is V pulled up to the internal bias voltage of 1.6V by a volt- VIN(FALLING) = 1.22 • (R3 +R4) R4 age divider (R1 and R2) connected from VOUT to SGND. Comparator A2 becomes inactive and comparator A1 VVIN(RISING) =2.2µA •R3+ VIN(FALLING) performs the inverting amplification from FBX to VC. When the LT3959 is in an inverting configuration, the FBX pin For applications where the EN/UVLO pin is only used as is pulled down to –0.8V by a voltage divider connected a logic input, the EN/UVLO pin can be connected directly from V to the input voltage V OUT to SGND. Comparator A1 becomes inactive and IN for always-on operation. 3959fa For more information www.linear.com/LT3959 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts